litex-boards/litex_boards/partner/platforms/netv2.py

103 lines
3.5 KiB
Python

# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [
# clock
("clk50", 0, Pins("J19"), IOStandard("LVCMOS33")),
# leds
("user_led", 0, Pins("M21"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("N20"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("L21"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("AA21"), IOStandard("LVCMOS33")),
("user_led", 4, Pins("R19"), IOStandard("LVCMOS33")),
("user_led", 5, Pins("M16"), IOStandard("LVCMOS33")),
# flash
("flash", 0,
Subsignal("cs_n", Pins("T19")),
Subsignal("mosi", Pins("P22")),
Subsignal("miso", Pins("R22")),
Subsignal("vpp", Pins("P21")),
Subsignal("hold", Pins("R21")),
IOStandard("LVCMOS33")
),
# serial
("serial", 0,
Subsignal("tx", Pins("E14")),
Subsignal("rx", Pins("E13")),
IOStandard("LVCMOS33"),
),
# dram
("ddram", 0,
Subsignal("a", Pins(
"U6 V4 W5 V5 AA1 Y2 AB1 AB3",
"AB2 Y3 W6 Y1 V2 AA3"
),
IOStandard("SSTL15")),
Subsignal("ba", Pins("U5 W4 V7"), IOStandard("SSTL15")),
Subsignal("ras_n", Pins("Y9"), IOStandard("SSTL15")),
Subsignal("cas_n", Pins("Y7"), IOStandard("SSTL15")),
Subsignal("we_n", Pins("V8"), IOStandard("SSTL15")),
Subsignal("dm", Pins("M5 L3"), IOStandard("SSTL15")),
Subsignal("dq", Pins(
"N2 M6 P1 N5 P2 N4 R1 P6 "
"K3 M2 K4 M3 J6 L5 J4 K6 "
),
IOStandard("SSTL15"),
Misc("IN_TERM=UNTUNED_SPLIT_50")),
Subsignal("dqs_p", Pins("P5 M1"), IOStandard("DIFF_SSTL15")),
Subsignal("dqs_n", Pins("P4 L1"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_p", Pins("R3"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_n", Pins("R2"), IOStandard("DIFF_SSTL15")),
Subsignal("cke", Pins("Y8"), IOStandard("SSTL15")),
Subsignal("odt", Pins("W9"), IOStandard("SSTL15")),
Subsignal("reset_n", Pins("AB5"), IOStandard("LVCMOS15")),
Subsignal("cs_n", Pins("V9"), IOStandard("SSTL15")),
Misc("SLEW=FAST"),
),
# ethernet
("eth_clocks", 0,
Subsignal("ref_clk", Pins("D17")),
IOStandard("LVCMOS33"),
),
("eth", 0,
Subsignal("rst_n", Pins("F16")),
Subsignal("rx_data", Pins("A20 B18")),
Subsignal("crs_dv", Pins("C20")),
Subsignal("tx_en", Pins("A19")),
Subsignal("tx_data", Pins("C18 C19")),
Subsignal("mdc", Pins("F14")),
Subsignal("mdio", Pins("F13")),
Subsignal("rx_er", Pins("B20")),
Subsignal("int_n", Pins("D21")),
IOStandard("LVCMOS33")
),
# sdcard
("sdcard", 0,
Subsignal("data", Pins("L15 L16 K14 M13"), Misc("PULLUP True")),
Subsignal("cmd", Pins("L13"), Misc("PULLUP True")),
Subsignal("clk", Pins("K18")),
IOStandard("LVCMOS33"), Misc("SLEW=FAST")
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk50"
default_clk_period = 20.0
def __init__(self):
XilinxPlatform.__init__(self, "xc7a35t-fgg484-2", _io, toolchain="vivado")