89 lines
2.8 KiB
Python
89 lines
2.8 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 Piotr Esden-Tempski <piotr@esden.net>
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# Copyright (c) 2021 Sylvain Munaut <tnt@246tNt.com>
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# Copyright (c) 2023 Michael Welling <mwelling@ieee.org>
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# SPDX-License-Identifier: BSD-2-Clause
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# ICE-V wireless
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from litex.build.dfu import DFUProg
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticeiCE40Platform
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# IOs ----------------------------------------------------------------------------------------------
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_io_v0 = [
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# Clk / Rst
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("clk12", 0, Pins("35"), IOStandard("LVCMOS33")),
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# Leds
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("user_led_n", 0, Pins("39"), IOStandard("LVCMOS33")),
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("user_led_n", 1, Pins("40"), IOStandard("LVCMOS33")),
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("user_led_n", 2, Pins("41"), IOStandard("LVCMOS33")),
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# Button
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("user_btn_n", 0, Pins("19"), IOStandard("LVCMOS33")),
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# USB
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("usb", 0,
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Subsignal("d_p", Pins("4")),
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Subsignal("d_n", Pins("3")),
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Subsignal("pullup", Pins("45")),
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IOStandard("LVCMOS33")
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),
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# Serial
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("serial", 0,
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Subsignal("rx", Pins("11")),
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Subsignal("tx", Pins("12"), Misc("PULLUP")),
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IOStandard("LVCMOS33")
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),
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# SPIFlash
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("spiflash", 0,
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Subsignal("cs_n", Pins("37"), IOStandard("LVCMOS33")),
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Subsignal("clk", Pins("28"), IOStandard("LVCMOS33")),
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Subsignal("mosi", Pins("26"), IOStandard("LVCMOS33")),
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Subsignal("miso", Pins("23"), IOStandard("LVCMOS33")),
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Subsignal("wp", Pins("25"), IOStandard("LVCMOS33")),
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Subsignal("hold", Pins("27"), IOStandard("LVCMOS33")),
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),
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("spiflash4x", 0,
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Subsignal("cs_n", Pins("37"), IOStandard("LVCMOS33")),
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Subsignal("clk", Pins("28"), IOStandard("LVCMOS33")),
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Subsignal("dq", Pins("26 23 25 27"), IOStandard("LVCMOS33")),
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors_v0 = [
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("PMOD1", "19 12 11 9 18 21 10 8"),
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("PMOD2", " 4 48 47 46 3 45 44 2"),
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("PMOD3", "42 43 32 13 38 36 31 20")
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(LatticeiCE40Platform):
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default_clk_name = "clk12"
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default_clk_period = 1e9/12e6
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def __init__(self, revision="v0", toolchain="icestorm"):
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assert revision in ["v0"]
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io, connectors = {
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"v0": (_io_v0, _connectors_v0),
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}[revision]
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LatticeiCE40Platform.__init__(self, "ice40-up5k-sg48", io, connectors, toolchain=toolchain)
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def create_programmer(self):
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return DFUProg(vid="1d50", pid="6146")
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def do_finalize(self, fragment):
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LatticeiCE40Platform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk12", loose=True), 1e9/12e6)
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