147 lines
5.9 KiB
Python
Executable File
147 lines
5.9 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2019 Sean Cross <sean@xobs.io>
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# Copyright (c) 2018 David Shah <dave@ds0.me>
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# Copyright (c) 2020 Piotr Esden-Tempski <piotr@esden.net>
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# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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# The iCEBreaker is the first open source iCE40 FPGA development board designed for teachers and
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# students: https://www.crowdsupply.com/1bitsquared/icebreaker-fpga
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# This target file provides a minimal LiteX SoC for the iCEBreaker with a CPU, its ROM (in SPI Flash),
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# its SRAM, close to the others LiteX targets. A more complete example of LiteX SoC for the iCEBreaker
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# with more features, examples to run C/Rust code on the RISC-V CPU and documentation can be found
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# at: https://github.com/icebreaker-fpga/icebreaker-litex-examples
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import os
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.platforms import icebreaker
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from litex.soc.cores.up5kspram import Up5kSPRAM
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from litex.soc.cores.spi_flash import SpiFlash
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from litex.soc.cores.clock import iCE40PLL
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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kB = 1024
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mB = 1024*kB
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_por = ClockDomain(reset_less=True)
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# # #
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# Clk/Rst
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clk12 = platform.request("clk12")
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rst_n = platform.request("user_btn_n")
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# Power On Reset
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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self.comb += self.cd_por.clk.eq(ClockSignal())
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self.comb += por_done.eq(por_count == 0)
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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# PLL
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self.submodules.pll = pll = iCE40PLL(primitive="SB_PLL40_PAD")
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self.comb += pll.reset.eq(~rst_n | self.rst)
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pll.register_clkin(clk12, 12e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=False)
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self.specials += AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked)
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platform.add_period_constraint(self.cd_sys.clk, 1e9/sys_clk_freq)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
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def __init__(self, bios_flash_offset, **kwargs):
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sys_clk_freq = int(24e6)
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platform = icebreaker.Platform()
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platform.add_extension(icebreaker.break_off_pmod)
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# Disable Integrated ROM/SRAM since too large for iCE40 and UP5K has specific SPRAM.
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kwargs["integrated_sram_size"] = 0
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kwargs["integrated_rom_size"] = 0
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# Set CPU variant / reset address
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kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on iCEBreaker",
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ident_version = True,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# 128KB SPRAM (used as SRAM) ---------------------------------------------------------------
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self.submodules.spram = Up5kSPRAM(size=128*kB)
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self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=128*kB))
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# SPI Flash --------------------------------------------------------------------------------
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self.add_spi_flash(mode="1x", dummy_cycles=8)
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# Add ROM linker region --------------------------------------------------------------------
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self.bus.add_region("rom", SoCRegion(
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origin = self.mem_map["spiflash"] + bios_flash_offset,
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size = 32*kB,
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linker = True)
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)
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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self.add_csr("leds")
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# Flash --------------------------------------------------------------------------------------------
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def flash(bios_flash_offset):
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from litex.build.lattice.programmer import IceStormProgrammer
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prog = IceStormProgrammer()
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prog.flash(bios_flash_offset, "build/icebreaker/software/bios/bios.bin")
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prog.flash(0x00000000, "build/icebreaker/gateware/icebreaker.bin")
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exit()
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on iCEBreaker")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--bios-flash-offset", default=0x40000, help="BIOS offset in SPI Flash (default: 0x40000)")
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parser.add_argument("--flash", action="store_true", help="Flash Bitstream")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(args.bios_flash_offset, **soc_core_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bin"))
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if args.flash:
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flash(args.bios_flash_offset)
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if __name__ == "__main__":
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main()
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