110 lines
4.0 KiB
Python
Executable File
110 lines
4.0 KiB
Python
Executable File
#!/usr/bin/env python3
|
|
|
|
import argparse
|
|
|
|
from migen import *
|
|
|
|
from litex_boards.official.platforms import genesys2
|
|
|
|
from litex.soc.cores.clock import *
|
|
from litex.soc.integration.soc_core import mem_decoder
|
|
from litex.soc.integration.soc_sdram import *
|
|
from litex.soc.integration.builder import *
|
|
|
|
from litedram.modules import MT41J256M16
|
|
from litedram.phy import s7ddrphy
|
|
|
|
from liteeth.phy.s7rgmii import LiteEthPHYRGMII
|
|
from liteeth.core.mac import LiteEthMAC
|
|
|
|
# CRG ----------------------------------------------------------------------------------------------
|
|
|
|
class _CRG(Module):
|
|
def __init__(self, platform, sys_clk_freq):
|
|
self.clock_domains.cd_sys = ClockDomain()
|
|
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
|
|
self.clock_domains.cd_clk200 = ClockDomain()
|
|
|
|
# # #
|
|
|
|
self.cd_sys.clk.attr.add("keep")
|
|
self.cd_sys4x.clk.attr.add("keep")
|
|
|
|
self.submodules.pll = pll = S7MMCM(speedgrade=-2)
|
|
self.comb += pll.reset.eq(~platform.request("cpu_reset_n"))
|
|
pll.register_clkin(platform.request("clk200"), 200e6)
|
|
pll.create_clkout(self.cd_sys, sys_clk_freq)
|
|
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
|
|
pll.create_clkout(self.cd_clk200, 200e6)
|
|
|
|
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
|
|
|
|
# BaseSoC ------------------------------------------------------------------------------------------
|
|
|
|
class BaseSoC(SoCSDRAM):
|
|
def __init__(self, sys_clk_freq=int(125e6), **kwargs):
|
|
platform = genesys2.Platform()
|
|
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
|
|
integrated_rom_size=0x8000,
|
|
integrated_sram_size=0x8000,
|
|
**kwargs)
|
|
|
|
self.submodules.crg = _CRG(platform, sys_clk_freq)
|
|
|
|
# sdram
|
|
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq)
|
|
self.add_csr("ddrphy")
|
|
sdram_module = MT41J256M16(self.clk_freq, "1:4")
|
|
self.register_sdram(self.ddrphy,
|
|
sdram_module.geom_settings,
|
|
sdram_module.timing_settings)
|
|
|
|
# EthernetSoC ------------------------------------------------------------------------------------------
|
|
|
|
class EthernetSoC(BaseSoC):
|
|
mem_map = {
|
|
"ethmac": 0x30000000, # (shadow @0xb0000000)
|
|
}
|
|
mem_map.update(BaseSoC.mem_map)
|
|
|
|
def __init__(self, **kwargs):
|
|
BaseSoC.__init__(self, **kwargs)
|
|
|
|
self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"),
|
|
self.platform.request("eth"))
|
|
self.add_csr("ethphy")
|
|
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
|
|
interface="wishbone", endianness=self.cpu.endianness)
|
|
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
|
|
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
|
|
self.add_csr("ethmac")
|
|
self.add_interrupt("ethmac")
|
|
|
|
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
|
|
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
|
|
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
|
|
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)
|
|
self.platform.add_false_path_constraints(
|
|
self.crg.cd_sys.clk,
|
|
self.ethphy.crg.cd_eth_rx.clk,
|
|
self.ethphy.crg.cd_eth_tx.clk)
|
|
|
|
# Build --------------------------------------------------------------------------------------------
|
|
|
|
def main():
|
|
parser = argparse.ArgumentParser(description="LiteX SoC on Genesys2")
|
|
builder_args(parser)
|
|
soc_sdram_args(parser)
|
|
parser.add_argument("--with-ethernet", action="store_true",
|
|
help="enable Ethernet support")
|
|
args = parser.parse_args()
|
|
|
|
cls = EthernetSoC if args.with_ethernet else BaseSoC
|
|
soc = cls(**soc_sdram_argdict(args))
|
|
builder = Builder(soc, **builder_argdict(args))
|
|
builder.build()
|
|
|
|
|
|
if __name__ == "__main__":
|
|
main()
|