115 lines
5.2 KiB
Python
Executable File
115 lines
5.2 KiB
Python
Executable File
#!/usr/bin/env python3
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import argparse
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from fractions import Fraction
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.official.platforms import minispartan6
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litedram.modules import AS4C16M16
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from litedram.phy import GENSDRPHY
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, clk_freq, use_s6pll=False):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys_ps = ClockDomain()
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# # #
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self.cd_sys.clk.attr.add("keep")
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self.cd_sys_ps.clk.attr.add("keep")
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if use_s6pll:
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self.submodules.pll = pll = S6PLL(speedgrade=-1)
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pll.register_clkin(platform.request("clk32"), 32e6)
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pll.create_clkout(self.cd_sys, clk_freq)
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pll.create_clkout(self.cd_sys_ps, clk_freq, phase=270)
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else:
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f0 = 32*1000000
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clk32 = platform.request("clk32")
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clk32a = Signal()
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self.specials += Instance("IBUFG", i_I=clk32, o_O=clk32a)
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clk32b = Signal()
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self.specials += Instance("BUFIO2", p_DIVIDE=1,
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p_DIVIDE_BYPASS="TRUE", p_I_INVERT="FALSE",
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i_I=clk32a, o_DIVCLK=clk32b)
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f = Fraction(int(clk_freq), int(f0))
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n, m, p = f.denominator, f.numerator, 8
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assert f0/n*m == clk_freq
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pll_lckd = Signal()
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pll_fb = Signal()
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pll = Signal(6)
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self.specials.pll = Instance("PLL_ADV", p_SIM_DEVICE="SPARTAN6",
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p_BANDWIDTH="OPTIMIZED", p_COMPENSATION="INTERNAL",
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p_REF_JITTER=.01, p_CLK_FEEDBACK="CLKFBOUT",
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i_DADDR=0, i_DCLK=0, i_DEN=0, i_DI=0, i_DWE=0, i_RST=0, i_REL=0,
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p_DIVCLK_DIVIDE=1, p_CLKFBOUT_MULT=m*p//n, p_CLKFBOUT_PHASE=0.,
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i_CLKIN1=clk32b, i_CLKIN2=0, i_CLKINSEL=1,
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p_CLKIN1_PERIOD=1000000000/f0, p_CLKIN2_PERIOD=0.,
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i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, o_LOCKED=pll_lckd,
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o_CLKOUT0=pll[0], p_CLKOUT0_DUTY_CYCLE=.5,
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o_CLKOUT1=pll[1], p_CLKOUT1_DUTY_CYCLE=.5,
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o_CLKOUT2=pll[2], p_CLKOUT2_DUTY_CYCLE=.5,
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o_CLKOUT3=pll[3], p_CLKOUT3_DUTY_CYCLE=.5,
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o_CLKOUT4=pll[4], p_CLKOUT4_DUTY_CYCLE=.5,
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o_CLKOUT5=pll[5], p_CLKOUT5_DUTY_CYCLE=.5,
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p_CLKOUT0_PHASE=0., p_CLKOUT0_DIVIDE=p//1,
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p_CLKOUT1_PHASE=0., p_CLKOUT1_DIVIDE=p//1,
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p_CLKOUT2_PHASE=0., p_CLKOUT2_DIVIDE=p//1,
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p_CLKOUT3_PHASE=0., p_CLKOUT3_DIVIDE=p//1,
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p_CLKOUT4_PHASE=0., p_CLKOUT4_DIVIDE=p//1, # sys
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p_CLKOUT5_PHASE=270., p_CLKOUT5_DIVIDE=p//1, # sys_ps
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)
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self.specials += Instance("BUFG", i_I=pll[4], o_O=self.cd_sys.clk)
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self.specials += Instance("BUFG", i_I=pll[5], o_O=self.cd_sys_ps.clk)
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self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_lckd)
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self.specials += Instance("ODDR2", p_DDR_ALIGNMENT="NONE",
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p_INIT=0, p_SRTYPE="SYNC",
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i_D0=0, i_D1=1, i_S=0, i_R=0, i_CE=1,
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i_C0=self.cd_sys.clk, i_C1=~self.cd_sys.clk,
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o_Q=platform.request("sdram_clock"))
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCSDRAM):
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def __init__(self, sys_clk_freq=int(80e6), **kwargs):
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assert sys_clk_freq == int(80e6)
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platform = minispartan6.Platform()
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SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
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integrated_rom_size=0x8000,
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**kwargs)
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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if not self.integrated_main_ram_size:
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self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
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sdram_module = AS4C16M16(sys_clk_freq, "1:1")
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self.register_sdram(self.sdrphy,
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sdram_module.geom_settings,
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sdram_module.timing_settings)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on MiniSpartan6")
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builder_args(parser)
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soc_sdram_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(**soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build()
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if __name__ == "__main__":
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main()
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