124 lines
4.7 KiB
Python
124 lines
4.7 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2024 Enjoy-Digital <enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticeNexusPlatform
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from litex.build.openfpgaloader import OpenFPGALoader
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Figure A.6
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("clk24", 0, Pins("M20"), IOStandard("LVCMOS18")),
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("clk27", 0, Pins("M22"), IOStandard("LVCMOS18")),
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# 8.1. General Purpose Push Buttons - all logic zero when pressed
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("gsrn", 0, Pins("R5"), IOStandard("LVCMOS33")), # SW4
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("programn", 0, Pins("C20"), IOStandard("LVCMOS33")), # SW5
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("user_btn", 0, Pins("N1"), IOStandard("LVCMOS33")), # SW2
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("user_btn", 1, Pins("N2"), IOStandard("LVCMOS33")), # SW3
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# 8.1. DIP Switch
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("user_dip_btn", 0, Pins("AA15"), IOStandard("LVCMOS33")),
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("user_dip_btn", 1, Pins("AB16"), IOStandard("LVCMOS33")),
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("user_dip_btn", 1, Pins("W16"), IOStandard("LVCMOS33")),
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# Figure 8.1 UART Topology
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("serial", 0,
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Subsignal("rx", Pins("E22"), IOStandard("LVCMOS33")),
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Subsignal("tx", Pins("D22"), IOStandard("LVCMOS33")),
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),
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# 7.1. General Purpose LEDs (Inverted)
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("user_led", 0, Pins("M6"), IOStandard("LVCMOS33")), # Bank 6 Green
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("user_led", 1, Pins("M7"), IOStandard("LVCMOS33")), # Bank 6 Green
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("user_led", 2, Pins("N6"), IOStandard("LVCMOS33")), # Bank 6 Green
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("user_led", 3, Pins("N5"), IOStandard("LVCMOS33")), # Bank 6 Green
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("rgb_led", 0,
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Subsignal("r", Pins("P2")), # Bank 6 LED4 Red
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Subsignal("g", Pins("P1")), # Bank 6 LED4 Green
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Subsignal("b", Pins("P3")), # Bank 6 LED4 Blue
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IOStandard("LVCMOS33")
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),
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("rgb_led", 1,
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Subsignal("r", Pins("R3")), # Bank 6 LED5 Red
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Subsignal("g", Pins("R4")), # Bank 6 LED5 Green
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Subsignal("b", Pins("P4")), # Bank 6 LED5 Blue
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IOStandard("LVCMOS33")
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),
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("spiflash", 0,
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Subsignal("cs_n", Pins("F17")),
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Subsignal("clk", Pins("F15")),
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Subsignal("mosi", Pins("E18")),
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Subsignal("miso", Pins("C21")),
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Subsignal("wp", Pins("C22")),
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Subsignal("hold", Pins("E16")),
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IOStandard("LVCMOS33")
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),
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("spiflash4x", 0,
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Subsignal("cs_n", Pins("F17")),
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Subsignal("clk", Pins("F15")),
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Subsignal("dq", Pins("E18 C21 C22 E16")),
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IOStandard("LVCMOS33")
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),
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# HyperRAM
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("hyperram", 0,
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Subsignal("dq", Pins("V18 W19 AB19 AB20 AB21 AB18 AA17 W18"), IOStandard("LVCMOS18H")),
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Subsignal("rwds", Pins("V19"), IOStandard("LVCMOS18H")),
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Subsignal("cs_n", Pins("AA18"), IOStandard("LVCMOS18H")),
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Subsignal("rst_n", Pins("AB17"), IOStandard("LVCMOS18H")),
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Subsignal("clk", Pins("Y19"), IOStandard("LVDS")),
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# Subsignal("clk_n", Pins("Y18"), IOStandard("LVDS")),
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Misc("SLEWRATE=FAST")
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),
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("hyperram", 1,
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Subsignal("dq", Pins("V22 AA20 V21 U21 U20 Y22 AA22 AA21"), IOStandard("LVCMOS18H")),
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Subsignal("rwds", Pins("Y21"), IOStandard("LVCMOS18H")),
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Subsignal("cs_n", Pins("AA19"), IOStandard("LVCMOS18H")),
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Subsignal("rst_n", Pins("U18"), IOStandard("LVCMOS18H")),
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Subsignal("clk", Pins("W22"), IOStandard("LVDS")),
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# Subsignal("clk_n", Pins("W21"), IOStandard("LVDS")),
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Misc("SLEWRATE=FAST")
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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# Table 6.2 PMOD Header
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# PMOD signal number:
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# 1 2 3 4 7 8 9 10
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("PMOD0", "L6 L8 L10 K10 J6 H6 H7 H8"),
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("PMOD1", "L1 K2 K3 J1 L2 M1 M2 K1"),
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("PMOD2", "L4 H1 G5 J9 L3 J2 H4 G7"),
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("PMOD3", "J7 K6 H5 K4 K8 J8 L9 K9"),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(LatticeNexusPlatform):
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default_clk_name = "clk24"
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default_clk_period = 1e9/24e6
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def __init__(self, device="LFCPNX", toolchain="radiant", **kwargs):
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assert device in ["LFCPNX"]
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LatticeNexusPlatform.__init__(self, device + "-100-9BBG484I", _io, _connectors, toolchain=toolchain, **kwargs)
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# SPI Pins may be used as General IO Pins (see FPGA-AN-02048 4.1.7)
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self.add_platform_command("ldc_set_sysconfig {{MASTER_SPI_PORT=DISABLE}}")
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# Evaluation mode (with free license)
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self.toolchain.set_prj_strategy_opts({"bit_ip_eval": "true"})
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def create_programmer(self):
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return OpenFPGALoader()
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def do_finalize(self, fragment):
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LatticeNexusPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk24", loose=True), 1e9/24e6)
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