58 lines
1.9 KiB
Python
58 lines
1.9 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2019 Antony Pavlov <antonynpavlov@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.altera import AlteraPlatform
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from litex.build.altera.programmer import USBBlaster
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk
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("clk50", 0, Pins("Y2"), IOStandard("3.3-V LVTTL")),
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# Serial
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("serial", 0,
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Subsignal("tx", Pins("G9"), IOStandard("3.3-V LVTTL")), # Use built-in Tx RS32 port
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Subsignal("rx", Pins("G12"), IOStandard("3.3-V LVTTL")) # Use built-in Rx RS32 port
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),
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# SDR SDRAM
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("sdram_clock", 0, Pins("AE5"), IOStandard("3.3-V LVTTL")),
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("sdram", 0,
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Subsignal("a", Pins(
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"R6 V8 U8 P1 V5 W8 W7 AA7",
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"Y5 Y6 R5 AA5 Y7")),
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Subsignal("ba", Pins("U7 R4")),
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Subsignal("cs_n", Pins("T4")),
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Subsignal("cke", Pins("AA6")),
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Subsignal("ras_n", Pins("U6")),
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Subsignal("cas_n", Pins("V7")),
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Subsignal("we_n", Pins("V6")),
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Subsignal("dq", Pins(
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"W3 W2 V4 W1 V3 V2 V1 U3",
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"Y3 Y4 AB1 AA3 AB2 AC1 AB3 AC2")),
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Subsignal("dm", Pins("U2 W4")),
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IOStandard("3.3-V LVTTL")
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(AlteraPlatform):
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default_clk_name = "clk50"
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default_clk_period = 1e9/50e6
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def __init__(self, toolchain="quartus"):
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AlteraPlatform.__init__(self, "EP4CE115F29C7", _io, toolchain=toolchain)
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def create_programmer(self):
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return USBBlaster()
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def do_finalize(self, fragment):
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AlteraPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
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