113 lines
4.1 KiB
Python
113 lines
4.1 KiB
Python
from litex_boards.partner.platforms import netv2
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from migen import Module, Signal, Instance, ClockDomain, If
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from migen.genlib.resetsync import AsyncResetSynchronizer
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, use_pll=True):
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clk48_raw = platform.request("clk48")
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clk12_raw = Signal()
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clk48 = Signal()
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clk12 = Signal()
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reset_delay = Signal(13, reset=4095)
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self.clock_domains.cd_por = ClockDomain()
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self.reset = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_usb_12 = ClockDomain()
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self.clock_domains.cd_usb_48 = ClockDomain()
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platform.add_period_constraint(self.cd_usb_48.clk, 1e9/48e6)
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platform.add_period_constraint(self.cd_sys.clk, 1e9/12e6)
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platform.add_period_constraint(self.cd_usb_12.clk, 1e9/12e6)
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platform.add_period_constraint(clk48, 1e9/48e6)
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platform.add_period_constraint(clk48_raw, 1e9/48e6)
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platform.add_period_constraint(clk12_raw, 1e9/12e6)
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# POR reset logic- POR generated from sys clk, POR logic feeds sys clk
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# reset.
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self.comb += [
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self.cd_por.clk.eq(self.cd_sys.clk),
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self.cd_sys.rst.eq(reset_delay != 0),
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self.cd_usb_12.rst.eq(reset_delay != 0),
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]
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if use_pll:
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# Divide clk48 down to clk12, to ensure they're synchronized.
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# By doing this, we avoid needing clock-domain crossing.
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clk12_counter = Signal(2)
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self.clock_domains.cd_usb_48_raw = ClockDomain()
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platform.add_period_constraint(self.cd_usb_48_raw.clk, 1e9/48e6)
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# POR reset logic- POR generated from sys clk, POR logic feeds sys clk
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# reset.
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self.comb += [
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self.cd_usb_48.rst.eq(reset_delay != 0),
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]
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self.comb += self.cd_usb_48_raw.clk.eq(clk48_raw)
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self.comb += self.cd_usb_48.clk.eq(clk48)
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self.sync.usb_48_raw += clk12_counter.eq(clk12_counter + 1)
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self.comb += clk12_raw.eq(clk12_counter[1])
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self.specials += Instance(
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"SB_GB",
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i_USER_SIGNAL_TO_GLOBAL_BUFFER=clk12_raw,
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o_GLOBAL_BUFFER_OUTPUT=clk12,
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)
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self.specials += Instance(
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"SB_PLL40_CORE",
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# Parameters
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p_DIVR = 0,
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p_DIVF = 3,
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p_DIVQ = 2,
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p_FILTER_RANGE = 1,
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p_FEEDBACK_PATH = "PHASE_AND_DELAY",
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p_DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED",
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p_FDA_FEEDBACK = 15,
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p_DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED",
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p_FDA_RELATIVE = 0,
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p_SHIFTREG_DIV_MODE = 1,
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p_PLLOUT_SELECT = "SHIFTREG_0deg",
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p_ENABLE_ICEGATE = 0,
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# IO
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i_REFERENCECLK = clk12,
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o_PLLOUTGLOBAL = clk48,
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i_BYPASS = 0,
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i_RESETB = 1,
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)
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else:
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self.specials += Instance(
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"SB_GB",
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i_USER_SIGNAL_TO_GLOBAL_BUFFER=clk48_raw,
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o_GLOBAL_BUFFER_OUTPUT=clk48,
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)
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self.comb += self.cd_usb_48.clk.eq(clk48)
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clk12_counter = Signal(2)
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self.sync.usb_48 += clk12_counter.eq(clk12_counter + 1)
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self.comb += clk12_raw.eq(clk12_counter[1])
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self.specials += Instance(
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"SB_GB",
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i_USER_SIGNAL_TO_GLOBAL_BUFFER=clk12_raw,
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o_GLOBAL_BUFFER_OUTPUT=clk12,
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)
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self.comb += self.cd_sys.clk.eq(clk12)
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self.comb += self.cd_usb_12.clk.eq(clk12)
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self.sync.por += \
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If(reset_delay != 0,
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reset_delay.eq(reset_delay - 1)
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)
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self.specials += AsyncResetSynchronizer(self.cd_por, self.reset)
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