182 lines
7.0 KiB
Python
Executable File
182 lines
7.0 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Ilia Sergachev <ilia@sergachev.ch>
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# SPDX-License-Identifier: BSD-2-Clause
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import argparse
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from migen import *
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from litex_boards.platforms import digilent_zedboard
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from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
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from litex.build.tools import write_to_file
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from litex.soc.interconnect import axi
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from litex.soc.interconnect import wishbone
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, use_ps7_clk=False):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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# # #
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if use_ps7_clk:
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self.comb += ClockSignal("sys").eq(ClockSignal("ps7"))
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self.comb += ResetSignal("sys").eq(ResetSignal("ps7") | self.rst)
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else:
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self.submodules.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(platform.request(platform.default_clk_name), platform.default_clk_freq)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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# Ignore sys_clk to pll.clkin path created by SoC's rst.
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq, with_led_chaser=True, **kwargs):
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platform = digilent_zedboard.Platform()
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if kwargs.get("cpu_type", None) == "zynq7000":
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kwargs['integrated_sram_size'] = 0
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on Zedboard",
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ident_version = True,
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**kwargs)
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# Zynq7000 Integration ---------------------------------------------------------------------
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if kwargs.get("cpu_type", None) == "zynq7000":
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self.cpu.set_ps7(name="Zynq",
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preset="ZedBoard",
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config={'PCW_FPGA0_PERIPHERAL_FREQMHZ': sys_clk_freq / 1e6})
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# Connect AXI GP0 to the SoC
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wb_gp0 = wishbone.Interface()
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self.submodules += axi.AXI2Wishbone(
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axi = self.cpu.add_axi_gp_master(),
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wishbone = wb_gp0,
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base_address = 0x43c0_0000) # default GP0 address on Zynq
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self.add_wb_master(wb_gp0)
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# FIXME: collection of hacks to enable BIOS compilation
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self.bus.add_region("sram", SoCRegion(
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origin=128 * 1024 * 1024,
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size=256 * 1024 * 1024)
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)
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self.bus.add_region("rom", SoCRegion(
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origin=256 * 1024 * 1024,
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size=8 * 1024 * 1024,
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linker=True)
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)
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self.cpu.use_rom = True
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self.constants['CONFIG_CLOCK_FREQUENCY'] = 666666687
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use_ps7_clk = True
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else:
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use_ps7_clk = False
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq, use_ps7_clk)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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def finalize(self, *args, **kwargs):
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super(BaseSoC, self).finalize(*args, **kwargs)
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if self.cpu_type != "zynq7000":
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return
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libxil_path = os.path.join(self.builder.software_dir, 'libxil')
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os.makedirs(os.path.realpath(libxil_path), exist_ok=True)
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lib = os.path.join(libxil_path, 'embeddedsw')
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if not os.path.exists(lib):
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os.system("git clone --depth 1 https://github.com/Xilinx/embeddedsw {}".format(lib))
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os.makedirs(os.path.realpath(self.builder.include_dir), exist_ok=True)
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for header in [
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'XilinxProcessorIPLib/drivers/uartps/src/xuartps_hw.h',
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'lib/bsp/standalone/src/common/xil_types.h',
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'lib/bsp/standalone/src/common/xil_assert.h',
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'lib/bsp/standalone/src/common/xil_io.h',
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'lib/bsp/standalone/src/common/xil_printf.h',
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'lib/bsp/standalone/src/common/xstatus.h',
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'lib/bsp/standalone/src/common/xdebug.h',
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'lib/bsp/standalone/src/arm/cortexa9/xpseudo_asm.h',
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'lib/bsp/standalone/src/arm/cortexa9/xreg_cortexa9.h',
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'lib/bsp/standalone/src/arm/cortexa9/xil_cache.h',
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'lib/bsp/standalone/src/arm/cortexa9/xparameters_ps.h',
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'lib/bsp/standalone/src/arm/cortexa9/xil_errata.h',
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'lib/bsp/standalone/src/arm/cortexa9/xtime_l.h',
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'lib/bsp/standalone/src/arm/common/xil_exception.h',
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'lib/bsp/standalone/src/arm/common/gcc/xpseudo_asm_gcc.h',
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]:
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shutil.copy(os.path.join(lib, header), self.builder.include_dir)
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write_to_file(os.path.join(self.builder.include_dir, 'bspconfig.h'),
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'#define FPU_HARD_FLOAT_ABI_ENABLED 1')
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write_to_file(os.path.join(self.builder.include_dir, 'xparameters.h'), '''
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#ifndef __XPARAMETERS_H
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#define __XPARAMETERS_H
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#include "xparameters_ps.h"
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#define STDOUT_BASEADDRESS 0xE0001000
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#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000
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#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x3FFFFFFF
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#endif
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''')
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Zedboard")
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parser.add_argument("--build", action="store_true", help="Build bitstream.")
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parser.add_argument("--load", action="store_true", help="Load bitstream.")
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parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
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builder_args(parser)
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soc_core_args(parser)
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vivado_build_args(parser)
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parser.set_defaults(cpu_type="zynq7000")
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parser.set_defaults(no_uart=True)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq=int(float(args.sys_clk_freq)),
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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if args.cpu_type == "zynq7000":
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soc.builder = builder
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builder.add_software_package('libxil')
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builder.add_software_library('libxil')
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builder.build(**vivado_build_argdict(args), run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
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if __name__ == "__main__":
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main()
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