177 lines
7.7 KiB
Python
Executable File
177 lines
7.7 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2022 Icenowy Zheng <icenowy@aosc.io>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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from migen import *
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from litex.gen import LiteXModule
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from litex_boards.platforms import sipeed_tang_nano_9k
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from litex.soc.cores.clock.gowin_gw1n import GW1NPLL
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.video import *
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from litex.soc.cores.hyperbus import HyperRAM
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kB = 1024
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mB = 1024*kB
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq, with_video_pll=False):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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# # #
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# Clk / Rst
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clk27 = platform.request("clk27")
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rst_n = platform.request("user_btn", 0)
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# PLL
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self.pll = pll = GW1NPLL(devicename=platform.devicename, device=platform.device)
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self.comb += pll.reset.eq(~rst_n)
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pll.register_clkin(clk27, 27e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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# Video PLL
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if with_video_pll:
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self.video_pll = video_pll = GW1NPLL(devicename=platform.devicename, device=platform.device)
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self.comb += video_pll.reset.eq(~rst_n)
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video_pll.register_clkin(clk27, 27e6)
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self.cd_hdmi = ClockDomain()
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self.cd_hdmi5x = ClockDomain()
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video_pll.create_clkout(self.cd_hdmi5x, 125e6)
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self.specials += Instance("CLKDIV",
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p_DIV_MODE= "5",
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i_RESETN = rst_n,
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i_HCLKIN = self.cd_hdmi5x.clk,
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o_CLKOUT = self.cd_hdmi.clk
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)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(27e6), bios_flash_offset=0x0,
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with_led_chaser=True, with_video_terminal=False, **kwargs):
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platform = sipeed_tang_nano_9k.Platform()
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq, with_video_pll=with_video_terminal)
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# SoCCore ----------------------------------------------------------------------------------
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# Disable Integrated ROM
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kwargs["integrated_rom_size"] = 0
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Tang Nano 9K", **kwargs)
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# SPI Flash --------------------------------------------------------------------------------
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from litespi.modules import W25Q32
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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self.add_spi_flash(mode="1x", module=W25Q32(Codes.READ_1_1_1), with_master=False)
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# Add ROM linker region --------------------------------------------------------------------
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self.bus.add_region("rom", SoCRegion(
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origin = self.bus.regions["spiflash"].origin + bios_flash_offset,
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size = 64*kB,
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linker = True)
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)
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self.cpu.set_reset_address(self.bus.regions["rom"].origin)
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# HyperRAM ---------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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# TODO: Use second 32Mbit PSRAM chip.
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dq = platform.request("IO_psram_dq")
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rwds = platform.request("IO_psram_rwds")
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reset_n = platform.request("O_psram_reset_n")
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cs_n = platform.request("O_psram_cs_n")
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ck = platform.request("O_psram_ck")
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ck_n = platform.request("O_psram_ck_n")
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class HyperRAMPads:
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def __init__(self, n):
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self.clk = Signal()
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self.rst_n = reset_n[n]
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self.dq = dq[8*n:8*(n+1)]
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self.cs_n = cs_n[n]
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self.rwds = rwds[n]
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hyperram_pads = HyperRAMPads(0)
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self.comb += ck[0].eq(hyperram_pads.clk)
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self.comb += ck_n[0].eq(~hyperram_pads.clk)
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# FIXME: Issue with upstream HyperRAM core, so use old one. Need to investigate.
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if not os.path.exists("hyperbus.py"):
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os.system("wget https://github.com/litex-hub/litex-boards/files/8831568/hyperbus.py.txt")
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os.system("mv hyperbus.py.txt hyperbus.py")
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from hyperbus import HyperRAM
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self.hyperram = HyperRAM(hyperram_pads)
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self.bus.add_slave("main_ram", slave=self.hyperram.bus, region=SoCRegion(origin=self.mem_map["main_ram"], size=4*mB))
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# Video ------------------------------------------------------------------------------------
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if with_video_terminal:
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self.videophy = VideoGowinHDMIPHY(platform.request("hdmi"), clock_domain="hdmi")
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self.add_video_colorbars(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi")
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#self.add_video_terminal(phy=self.videophy, timings="640x480@75Hz", clock_domain="hdmi") # FIXME: Free up BRAMs.
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXSoCArgumentParser(description="LiteX SoC on Tang Nano 9K")
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target_group = parser.add_argument_group(title="Target options")
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target_group.add_argument("--build", action="store_true", help="Build design.")
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target_group.add_argument("--load", action="store_true", help="Load bitstream.")
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target_group.add_argument("--flash", action="store_true", help="Flash Bitstream.")
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target_group.add_argument("--sys-clk-freq", default=27e6, help="System clock frequency.")
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target_group.add_argument("--bios-flash-offset", default="0x0", help="BIOS offset in SPI Flash.")
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target_group.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
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target_group.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
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target_group.add_argument("--prog-kit", default="openfpgaloader", help="Programmer select from Gowin/openFPGALoader.")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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bios_flash_offset = int(args.bios_flash_offset, 0),
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with_video_terminal = args.with_video_terminal,
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**soc_core_argdict(args)
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)
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if args.with_spi_sdcard:
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soc.add_spi_sdcard()
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builder = Builder(soc, **builder_argdict(args))
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if args.build:
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builder.build()
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if args.load:
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prog = soc.platform.create_programmer(kit=args.prog_kit)
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if args.flash:
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prog = soc.platform.create_programmer(kit=args.prog_kit)
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prog.flash(0, builder.get_bitstream_filename(mode="flash", ext=".fs")) # FIXME
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# Axternal SPI programming not supported by gowin 'programmer_cli' now!
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# if needed, use openFPGALoader or Gowin programmer GUI
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if args.prog_kit == "openfpgaloader":
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prog.flash(int(args.bios_flash_offset, 0), builder.get_bios_filename(), external=True)
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if __name__ == "__main__":
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main()
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