86 lines
3.0 KiB
Python
86 lines
3.0 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2022 FAYE Joseph <joseph-wagane.faye@insa-rennes.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import Xilinx7SeriesPlatform, VivadoProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk125", 0,
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Subsignal("p", Pins("G21"), IOStandard("LVDS")),
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Subsignal("n", Pins("F21"), IOStandard("LVDS")),
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),
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("clk300", 0,
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Subsignal("p", Pins("AL8"), IOStandard("DIFF_SSTL12_DCI")),
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Subsignal("n", Pins("AL7"), IOStandard("DIFF_SSTL12_DCI")),
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),
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("cpu_reset", 0, Pins("AM13"), IOStandard("LVCMOS33")),
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# Leds
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("user_led", 0, Pins("AG14"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("AF13"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("AE13"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("AJ14"), IOStandard("LVCMOS33")),
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("user_led", 4, Pins("AJ15"), IOStandard("LVCMOS33")),
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("user_led", 5, Pins("AH13"), IOStandard("LVCMOS33")),
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("user_led", 6, Pins("AH14"), IOStandard("LVCMOS33")),
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("user_led", 7, Pins("AL12"), IOStandard("LVCMOS33")),
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# Buttons
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("user_btn", 0, Pins("AG15"), IOStandard("LVCMOS33")),
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("user_btn", 1, Pins("AE14"), IOStandard("LVCMOS33")),
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("user_btn", 2, Pins("AF15"), IOStandard("LVCMOS33")),
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("user_btn", 3, Pins("AE15"), IOStandard("LVCMOS33")),
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("user_btn", 3, Pins("AG13"), IOStandard("LVCMOS33")),
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# Switches
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("user_dip", 0, Pins("AN14"), IOStandard("LVCMOS33")),
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("user_dip", 1, Pins("AP14"), IOStandard("LVCMOS33")),
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("user_dip", 2, Pins("AM14"), IOStandard("LVCMOS33")),
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("user_dip", 3, Pins("AN13"), IOStandard("LVCMOS33")),
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("user_dip", 4, Pins("AN12"), IOStandard("LVCMOS33")),
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("user_dip", 5, Pins("AP12"), IOStandard("LVCMOS33")),
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("user_dip", 6, Pins("AL13"), IOStandard("LVCMOS33")),
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("user_dip", 7, Pins("AK13"), IOStandard("LVCMOS33")),
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# Serial
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("serial", 0,
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Subsignal("cts", Pins("E12")),
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Subsignal("rts", Pins("D12")),
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Subsignal("tx", Pins("E13")),
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Subsignal("rx", Pins("F13")),
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IOStandard("LVCMOS18")
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),
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# I2C
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("i2c", 0,
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Subsignal("sda", Pins("J11")),
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Subsignal("scl", Pins("J10")),
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IOStandard("LVCMOS33")
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(Xilinx7SeriesPlatform):
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default_clk_name = "clk125"
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default_clk_period = 1e9/125e6
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def __init__(self, toolchain="vivado"):
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Xilinx7SeriesPlatform.__init__(self, "xczu9eg-ffvb1156-2-i", _io, toolchain=toolchain)
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def create_programmer(self):
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return VivadoProgrammer()
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def do_finalize(self, fragment):
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Xilinx7SeriesPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk125", loose=True), 1e9/125e6)
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self.add_period_constraint(self.lookup_request("clk300", loose=True), 1e9/300e6)
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