81 lines
2.7 KiB
Python
Executable File
81 lines
2.7 KiB
Python
Executable File
#!/usr/bin/env python3
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# This file is Copyright (c) 2013-2014 Sebastien Bourdeauducq <sb@m-labs.hk>
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# This file is Copyright (c) 2014-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2014 Yann Sionneau <ys@m-labs.hk>
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# License: BSD
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import argparse
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from fractions import Fraction
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.platforms import minispartan6
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litedram.modules import AS4C16M16
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from litedram.phy import GENSDRPHY
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys_ps = ClockDomain()
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# # #
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self.cd_sys.clk.attr.add("keep")
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self.cd_sys_ps.clk.attr.add("keep")
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self.submodules.pll = pll = S6PLL(speedgrade=-1)
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pll.register_clkin(platform.request("clk32"), 32e6)
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pll.create_clkout(self.cd_sys, clk_freq)
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pll.create_clkout(self.cd_sys_ps, clk_freq, phase=270)
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self.specials += Instance("ODDR2",
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p_DDR_ALIGNMENT="NONE",
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p_INIT=0, p_SRTYPE="SYNC",
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i_D0=0, i_D1=1, i_S=0, i_R=0, i_CE=1,
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i_C0=self.cd_sys.clk, i_C1=~self.cd_sys.clk,
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o_Q=platform.request("sdram_clock"))
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCSDRAM):
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def __init__(self, sys_clk_freq=int(80e6), **kwargs):
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assert sys_clk_freq == int(80e6)
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platform = minispartan6.Platform()
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SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
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integrated_rom_size=0x8000,
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**kwargs)
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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if not self.integrated_main_ram_size:
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self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
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sdram_module = AS4C16M16(sys_clk_freq, "1:1")
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self.register_sdram(self.sdrphy,
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sdram_module.geom_settings,
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sdram_module.timing_settings)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on MiniSpartan6")
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builder_args(parser)
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soc_sdram_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(**soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build()
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if __name__ == "__main__":
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main()
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