169 lines
6.4 KiB
Python
169 lines
6.4 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 Gary Wong <gtw@gnu.org>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticePlatform
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from litex.build.lattice.programmer import OpenOCDJTAGProgrammer
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import os
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clock
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("clk25", 0, Pins("P3"), IOStandard("LVCMOS33")),
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# LEDs
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("user_led", 0, Pins("N16"), IOStandard("LVCMOS15"), Misc( "OPENDRAIN=ON" ) ),
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("user_led", 1, Pins("P20"), IOStandard("LVCMOS15"), Misc( "OPENDRAIN=ON" ) ),
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("user_led", 2, Pins("R20"), IOStandard("LVCMOS15"), Misc( "OPENDRAIN=ON" ) ),
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("user_led", 3, Pins("N20"), IOStandard("LVCMOS15"), Misc( "OPENDRAIN=ON" ) ),
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("user_led", 4, Pins("U20"), IOStandard("LVCMOS15"), Misc( "OPENDRAIN=ON" ) ),
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("user_led", 5, Pins("M20"), IOStandard("LVCMOS15"), Misc( "OPENDRAIN=ON" ) ),
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("user_led", 6, Pins("T20"), IOStandard("LVCMOS15"), Misc( "OPENDRAIN=ON" ) ),
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("user_led", 7, Pins("D6"), IOStandard("LVCMOS33"), Misc( "OPENDRAIN=ON" ) ),
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# Serial
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#("serial", 0,
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# Subsignal("rx", Pins("N2"), IOStandard("LVCMOS33")),
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# Subsignal("tx", Pins("M1"), IOStandard("LVCMOS33"))),
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# USB FIFO
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("usb_fifo", 0,
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Subsignal( "data", Pins( "N2 M1 M3 L1 L2 K1 K2 J1" ) ),
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Subsignal( "rxf_n", Pins( "H1" ) ),
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Subsignal( "txe_n", Pins( "H2" ) ),
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Subsignal( "rd_n", Pins( "G1" ) ),
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Subsignal( "wr_n", Pins( "G2" ) ),
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Subsignal( "siwua", Pins( "F1" ) )
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),
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# SPIFlash
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("spiflash", 0,
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Subsignal("cs_n", Pins("R2"), IOStandard("LVCMOS33")),
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Subsignal("mosi", Pins("W2"), IOStandard("LVCMOS33")),
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Subsignal("miso", Pins("V2"), IOStandard("LVCMOS33")),
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Subsignal("wp", Pins("Y2"), IOStandard("LVCMOS33")),
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Subsignal("hold", Pins("W1"), IOStandard("LVCMOS33")),
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),
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("spiflash4x", 0,
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Subsignal("cs_n", Pins("R2"), IOStandard("LVCMOS33")),
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Subsignal("dq", Pins("W2 V2 Y2 W1"), IOStandard("LVCMOS33")),
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),
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# SDCard
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("spisdcard", 0,
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Subsignal("clk", Pins("A9")),
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Subsignal("mosi", Pins("E9"), Misc("PULLMODE=UP")),
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Subsignal("cs_n", Pins("B8"), Misc("PULLMODE=UP")),
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Subsignal("miso", Pins("D9"), Misc("PULLMODE=UP")),
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Misc("SLEWRATE=FAST"),
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IOStandard("LVCMOS33"),
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),
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("sdcard", 0,
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Subsignal("clk", Pins("A9")),
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Subsignal("cmd", Pins("E9"), Misc("PULLMODE=UP")),
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Subsignal("data", Pins("D9 B9 C8 B8"), Misc("PULLMODE=UP")),
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Misc("SLEWRATE=FAST"),
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IOStandard("LVCMOS33"),
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),
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# USB ULPI
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("ulpi", 0,
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Subsignal("clk", Pins("C6")),
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Subsignal("stp", Pins("D7")),
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Subsignal("dir", Pins("A7")),
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Subsignal("nxt", Pins("C7")),
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Subsignal("reset", Pins("D8")),
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Subsignal("data", Pins("A5 B5 A4 B4 A3 B3 A2 B2")),
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IOStandard("LVCMOS33")
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),
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# DDR3 SDRAM
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("dram_vtt_en", 0, Pins( "M19" ), IOStandard( "LVCMOS15" ), Misc( "OPENDRAIN=ON" ) ),
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("ddram", 0,
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Subsignal( "a", Pins( "E18 H16 D18 L16 H17 E17 G18 C18 "
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"G16 D17 J16 F18 J17 F16 F17" ),
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IOStandard( "SSTL15_I" ) ),
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Subsignal( "ba", Pins( "M18 H18 L17" ), IOStandard( "SSTL15_I" ) ),
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Subsignal( "ras_n", Pins( "R17" ), IOStandard( "SSTL15_I" ) ),
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Subsignal( "cas_n", Pins( "R16" ), IOStandard( "SSTL15_I" ) ),
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Subsignal( "we_n", Pins( "M17" ), IOStandard( "SSTL15_I" ) ),
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Subsignal( "cs_n", Pins( "P17" ), IOStandard( "SSTL15_I" ) ),
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Subsignal( "dm", Pins( "F20 T18" ), IOStandard( "SSTL15_I" ) ),
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Subsignal( "dq", Pins( "J20 F19 J19 E19 K19 E20 K20 G20 ",
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"T17 U16 P18 U17 N19 U18 P19 U19" ),
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IOStandard( "SSTL15_I" ), Misc( "TERMINATION=50" ) ),
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Subsignal( "dqs_p", Pins( "G19 T19" ), IOStandard( "SSTL15D_I" ),
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Misc( "TERMINATION=OFF" ), Misc( "DIFFRESISTOR=100" ) ),
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Subsignal( "clk_p", Pins( "K16" ), IOStandard( "SSTL15D_I" ) ),
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Subsignal( "cke", Pins( "D19" ), IOStandard( "SSTL15_I" ) ),
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Subsignal( "odt", Pins( "H4" ) ), # FIXME not connected
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Subsignal( "reset_n", Pins( "L20" ), IOStandard( "SSTL15_I" ) ),
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# Pseudo-VCCIO pads: SSTL15_II for 10 mA drive strength, see
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# FPGA-TN-02035, section 6.7.
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Subsignal( "vccio", Pins( "C20 E16 J18 K18 L18 L19 N17 N18 T16" ),
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IOStandard( "SSTL15_II" ) ),
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Misc( "SLEWRATE=FAST" ) ),
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# MII Ethernet
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("eth_clocks", 0,
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Subsignal("rx", Pins("L5")),
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Subsignal("tx", Pins("P1")),
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IOStandard("LVCMOS33"),
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),
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("eth", 0,
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Subsignal("rx_data", Pins("N3 N4 N5 P4")),
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Subsignal("rx_dv", Pins("M5")),
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Subsignal("tx_data", Pins("N1 L4 L3 K4")),
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Subsignal("tx_en", Pins("P2")),
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Subsignal("mdc", Pins("P5")),
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Subsignal("mdio", Pins("J5")),
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Subsignal("rx_er", Pins("K5")),
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Subsignal("int_n", Pins("M4")),
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Subsignal("rst_n", Pins("C9")), # FIXME not connected
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IOStandard("LVCMOS33")
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),
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# HDMI output
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("hdmi", 0,
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Subsignal( "data0", Pins( "G3" ) ),
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Subsignal( "data1", Pins( "F4" ) ),
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Subsignal( "data2", Pins( "C1" ) ),
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Subsignal( "clk", Pins( "E4" ) ),
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IOStandard( "LVCMOS33D" ), Misc( "DRIVE=8 SLEWRATE=FAST" ) ),
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# USB host 1
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("usbhost", 0,
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Subsignal( "dp", Pins( "B6" ) ),
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Subsignal( "dn", Pins( "A6" ) ),
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IOStandard( "LVCMOS33" ) )
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(LatticePlatform):
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default_clk_name = "clk25"
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default_clk_period = 1e9/25e6
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def __init__(self, toolchain="trellis", **kwargs):
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LatticePlatform.__init__(self, "LFE5U-85F-8BG381", _io, _connectors, toolchain=toolchain, **kwargs)
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def request(self, *args, **kwargs):
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return LatticePlatform.request(self, *args, **kwargs)
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def create_programmer(self):
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return OpenOCDJTAGProgrammer("openocd_fpc_iii.cfg")
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def do_finalize(self, fragment):
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LatticePlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk25", loose=True), 1e9/25e6)
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