Paul Sajna 5091a1b40a WIP sdram module option		2020-01-29 13:59:57 -08:00
..
__init__.py	import: allow importing directly from litex_boards.platforms or litex_boards.targets	2019-09-03 15:30:20 +02:00
ac701.py	targets: cleanup EthernetSoC	2020-01-16 10:28:09 +01:00
de1soc.py	targets: use default integrated rom/ram size passed with **kwargs from default soc_core_args	2020-01-13 15:20:37 +01:00
de2_115.py	targets: use default integrated rom/ram size passed with **kwargs from default soc_core_args	2020-01-13 15:20:37 +01:00
de10lite.py	targets: use default integrated rom/ram size passed with **kwargs from default soc_core_args	2020-01-13 15:20:37 +01:00
de10nano.py	WIP sdram module option	2020-01-29 13:59:57 -08:00
ecp5_evn.py	targets: use default integrated rom/ram size passed with **kwargs from default soc_core_args	2020-01-13 15:20:37 +01:00
kx2.py	kx2: cleanup, fix copyright	2020-01-13 17:22:33 +01:00
mimas_a7.py	mimas_v7: cleanup, make it similar to others boards	2020-01-16 11:24:09 +01:00
pipistrello.py	targets: use default integrated rom/ram size passed with **kwargs from default soc_core_args	2020-01-13 15:20:37 +01:00