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enjoy-digital 53d5ed1226
Merge pull request #19 from lolsborn/ulx3s-target 
add sys clock freq flag, uses same method as current versa code
 		2019-10-13 10:32:43 +02:00
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platforms partners: fomu-evt: add "dbg" connector 2019-10-11 21:39:19 +08:00
targets Merge pull request #19 from lolsborn/ulx3s-target 2019-10-13 10:32:43 +02:00
__init__.py Turn litex_boards.partner into module 2019-07-01 19:36:34 +02:00