126 lines
4.7 KiB
Python
Executable File
126 lines
4.7 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2023 Nimalan M <nimalan.m@protonmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from litex.gen import *
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from litex_boards.platforms import alchitry_cu
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.cores.clock import iCE40PLL
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from litex.soc.cores.led import LedChaser
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from migen.genlib.resetsync import AsyncResetSynchronizer
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kB = 1024
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mB = 1024*kB
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# CRG -------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_por = ClockDomain()
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# Clk/Rst
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clk100 = platform.request("clk100")
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rst_n = platform.request("cpu_reset")
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# Power On Reset
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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self.comb += self.cd_por.clk.eq(ClockSignal())
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self.comb += por_done.eq(por_count == 0)
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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self.pll = pll = iCE40PLL(primitive="SB_PLL40_CORE")
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self.comb += pll.reset.eq(~rst_n) # FIXME: Add proper iCE40PLL reset support and add back | self.rst.
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pll.register_clkin(clk100, 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=False)
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self.specials += AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked)
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platform.add_period_constraint(self.cd_sys.clk, 1e9/sys_clk_freq)
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# BaseSoC -----------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self,
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bios_flash_offset,
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sys_clk_freq=50e6,
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with_led_chaser = True,
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**kwargs):
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# Create our platform (fpga interface)
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platform = alchitry_cu.Platform()
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# Disable Integrated ROM since too large for iCE40.
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kwargs["integrated_rom_size"] = 0
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# SoC with CPU
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on Alchitry Cu",
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**kwargs)
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# CRG
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# SPI Flash --------------------------------------------------------------------------------
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from litespi.modules import W25Q32
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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self.add_spi_flash(mode="1x", module=W25Q32(Codes.READ_1_1_1), with_master=False)
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# Add ROM linker region --------------------------------------------------------------------
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self.bus.add_region("rom", SoCRegion(
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origin = self.bus.regions["spiflash"].origin + bios_flash_offset,
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size = 256*kB,
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linker = True)
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)
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self.cpu.set_reset_address(self.bus.regions["rom"].origin)
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# Led
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if with_led_chaser:
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self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq)
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# Flash --------------------------------------------------------------------------------------------
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def flash(build_dir, build_name, bios_flash_offset):
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from litex.build.lattice.programmer import IceStormProgrammer
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prog = IceStormProgrammer()
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prog.flash(bios_flash_offset, f"{build_dir}/software/bios/bios.bin")
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prog.flash(0x00000000, f"{build_dir}/gateware/{build_name}.bin")
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=alchitry_cu.Platform, description="LiteX SoC on Alchitry Cu")
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parser.add_target_argument("--flash", action="store_true", help="Flash Bitstream and BIOS.")
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parser.add_target_argument("--bios-flash-offset", default="0x040000", help="BIOS offset in SPI Flash (default: 0x40000)")
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parser.add_target_argument("--sys-clk-freq", default=50e6, type=float, help="System clock frequency (default: 50MHz)")
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parser.add_target_argument("--with-led-chaser", action="store_true", help="Enable LED Chaser.")
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args = parser.parse_args()
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soc = BaseSoC(
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bios_flash_offset = int(args.bios_flash_offset, 0),
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sys_clk_freq = args.sys_clk_freq,
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**parser.soc_argdict
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)
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.flash:
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flash(builder.output_dir, soc.build_name, args.bios_flash_offset)
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if __name__ == "__main__":
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main()
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