202 lines
7.9 KiB
Python
202 lines
7.9 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 Hans Baier <hansfbaier@gmail.com>
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#
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.altera import AlteraPlatform
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from litex.build.altera.programmer import USBBlaster
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from litex.build.generic_platform import Pins, IOStandard, Subsignal, Misc
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk
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("clk50", 0, Pins("AF14"), IOStandard("3.3-V LVTTL")),
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# Leds
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("user_led", 0, Pins("AF10"), IOStandard("3.3-V LVTTL")),
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("user_led", 1, Pins("AD10"), IOStandard("3.3-V LVTTL")),
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("user_led", 2, Pins("AE11"), IOStandard("3.3-V LVTTL")),
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("user_led", 3, Pins("AD7"), IOStandard("3.3-V LVTTL")),
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# Buttons
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("user_btn", 0, Pins("AE9"), IOStandard("3.3-V LVTTL")),
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("user_btn", 1, Pins("AE12"), IOStandard("3.3-V LVTTL")),
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("user_btn", 2, Pins("AD9"), IOStandard("3.3-V LVTTL")),
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("user_btn", 3, Pins("AD11"), IOStandard("3.3-V LVTTL")),
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# Switches
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("user_sw", 0, Pins("W25"), IOStandard("3.3-V LVTTL")),
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("user_sw", 1, Pins("V25"), IOStandard("3.3-V LVTTL")),
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("user_sw", 2, Pins("AC28"), IOStandard("3.3-V LVTTL")),
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("user_sw", 3, Pins("AC29"), IOStandard("3.3-V LVTTL")),
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# MiSTer SDRAM via GPIO expansion board J2
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("sdram_clock", 0, Pins("D10"), IOStandard("3.3-V LVTTL")),
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("sdram", 0,
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Subsignal("a", Pins(
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"B1 C2 B2 D2 D9 C7 E12 B7",
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"D12 A11 B6 D11 A10")),
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Subsignal("ba", Pins("B5 A4")),
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Subsignal("cs_n", Pins("A3")),
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# CKE not connected on XS 2.2/2.4
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Subsignal("cke", Pins("B3")),
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Subsignal("ras_n", Pins("E9")),
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Subsignal("cas_n", Pins("A6")),
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Subsignal("we_n", Pins("A5")),
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Subsignal("dq", Pins(
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"F14 G15 F15 H15 G13 A13 H14 B13",
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"C13 C8 B12 B8 F13 C12 B11 E13"),
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),
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# DQML/DQMH not connected on XS 2.2/2.4
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Subsignal("dm", Pins("AB27 AA26")),
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IOStandard("3.3-V LVTTL"),
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Misc("CURRENT_STRENGTH_NEW \"MAXIMUM CURRENT\""),
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),
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# DDR3 SDRAM
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("ddram", 0,
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Subsignal("a", Pins(
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"AJ14 AK14 AH12 AJ12 AG15 AH15 AK12 AK13",
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"AH13 AH14 AJ9 AK9 AK7 AK8 AG12"),
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IOStandard("SSTL15"),
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),
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Subsignal("ba", Pins("AH10 AJ11 AK11"), IOStandard("SSTL-15 CLASS I"), ),
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Subsignal("ras_n", Pins("AH8"), IOStandard("SSTL-15 CLASS I")),
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Subsignal("cas_n", Pins("AH7"), IOStandard("SSTL-15 CLASS I")),
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Subsignal("we_n", Pins("AJ6"), IOStandard("SSTL-15 CLASS I")),
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Subsignal("dm", Pins("AH17 AG23 AK23 AJ27"),
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IOStandard("SSTL-15 CLASS I"),
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Misc("OUTPUT_TERMINATION=SERIES 50 OHM WITH CALIBRATION")
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),
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Subsignal("dq", Pins(
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"AF18 AE17 AG16 AF16 AH20 AG21 AJ16 AH18",
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"AK18 AJ17 AG18 AK19 AG20 AF19 AJ20 AH24",
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"AE19 AE18 AG22 AK22 AF21 AF20 AH23 AK24",
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"AF24 AF23 AJ24 AK26 AE23 AE22 AG25 AK27"),
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IOStandard("SSTL-15 CLASS I"),
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Misc("INPUT_TERMINATION=PARALLEL 50 OHM WITH CALIBRATION"),
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Misc("OUTPUT_TERMINATION=SERIES 50 OHM WITH CALIBRATION"),
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),
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Subsignal("dqs_p", Pins("V16 V17 Y17 AC20"),
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IOStandard("DIFFERENTIAL 1.5-V SSTL CLASS I"),
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Misc("INPUT_TERMINATION=PARALLEL 50 OHM WITH CALIBRATION"),
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Misc("OUTPUT_TERMINATION=SERIES 50 OHM WITH CALIBRATION")
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),
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Subsignal("dqs_n", Pins("W16 W17 AA18 AD19"),
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IOStandard("DIFFERENTIAL 1.5-V SSTL CLASS I"),
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Misc("INPUT_TERMINATION=PARALLEL 50 OHM WITH CALIBRATION"),
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Misc("OUTPUT_TERMINATION=SERIES 50 OHM WITH CALIBRATION")
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),
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Subsignal("clk_p", Pins("AA14"),
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IOStandard("DIFFERENTIAL 1.5-V SSTL CLASS I"),
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Misc("OUTPUT_TERMINATION=SERIES 50 OHM WITH CALIBRATION"),
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Misc("D5_DELAY=2")
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),
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Subsignal("clk_n", Pins("AA15"),
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IOStandard("DIFFERENTIAL 1.5-V SSTL CLASS I"),
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Misc("OUTPUT_TERMINATION=SERIES 50 OHM WITH CALIBRATION"),
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Misc("D5_DELAY=2")
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),
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Subsignal("cs_n", Pins("AB15"), IOStandard("SSTL-15 CLASS I")),
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Subsignal("cke", Pins("AJ21"), IOStandard("SSTL-15 CLASS I")),
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Subsignal("odt", Pins("AE16"), IOStandard("SSTL-15 CLASS I")),
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Subsignal("reset_n", Pins("AK21"), IOStandard("SSTL-15 CLASS I")),
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Subsignal("rzq", Pins("AG1"), IOStandard("SSTL-15")),
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Misc("CURRENT_STRENGTH_NEW=MAXIMUM CURRENT")
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),
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# VGA
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("vga", 0,
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Subsignal("hsync_n", Pins("AD12")),
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Subsignal("vsync_n", Pins("AC12")),
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Subsignal("sync_n", Pins("AG2")),
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Subsignal("blank_n", Pins("AH3")),
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Subsignal("r", Pins("AG5 AA12 AB12 AF6 AG6 AJ2 AH5 AJ1")),
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Subsignal("g", Pins("Y21 AA25 AB26 AB22 AB23 AA24 AB25 AE27")),
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Subsignal("b", Pins("AE28 Y23 Y24 AG28 AF28 V23 W24 AF29")),
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IOStandard("3.3-V LVTTL")
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),
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# IrDA
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("irda", 0,
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Subsignal("irda_rxd", Pins("AH2")),
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IOStandard("3.3-V LVTTL")
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),
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# Temperatue
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("temperature", 0,
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Subsignal("temp_cs_n", Pins("AF8")),
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Subsignal("temp_din", Pins("AG7")),
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Subsignal("temp_dout", Pins("AG1")),
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Subsignal("temp_sclk", Pins("AF9")),
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IOStandard("3.3-V LVTTL")
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),
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# Audio
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("audio", 0,
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Subsignal("aud_adclrck", Pins("AG30")),
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Subsignal("aud_adcdat", Pins("AC27")),
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Subsignal("aud_daclrck", Pins("AH4")),
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Subsignal("aud_dacdat", Pins("AG3")),
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Subsignal("aud_xck", Pins("AC9")),
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Subsignal("aud_bclk", Pins("AE7")),
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Subsignal("aud_i2c_sclk", Pins("AH30")),
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Subsignal("aud_i2c_sdat", Pins("AF30")),
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Subsignal("aud_mute", Pins("AD26")),
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IOStandard("3.3-V LVTTL")
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),
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("gpio_serial", 0,
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Subsignal("tx", Pins("J3:9")),
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Subsignal("rx", Pins("J3:10")),
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IOStandard("3.3-V LVTTL"))
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]
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# Connectors ---------------------------------------------------------------------------------------
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# Since the numbering of the connectors in the documentation is 1-based
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# I added a dummy pin (-) to the beginning to each connector
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# to make the numbering in the code consistent with the documentation
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_connectors_hsmc_gpio_daughterboard = [
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("J2", "- G15 F14 H15 F15 A13 G13 B13 H14 B11 E13 - - " +
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"C12 F13 B8 B12 C8 C13 A10 D10 A11 D11 B7 D12 C7 E12 A5 D9 - - " +
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"A6 E9 A3 B5 A4 B6 B1 C2 B2 D2"),
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("J2p", "- D1 E1 E11 F11"), # top to bottom, starting with 57
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("J3", "- AB27 F8 AA26 F9 B3 G8 C3 H8 D4 H7 - - " +
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"E4 J7 E2 K8 E3 K7 E6 J9 E7 J10 C4 J12 D5 G10 C5 J12 - - " +
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"D6 K12 F6 G11 G7 G12 D7 A8 E8 A9"),
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("J3p", "- C9 C10 H12 H13"), # top to bottom, starting with 117
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("J4", "- - - AD3 AE1 AD4 AE2 - - AB3 AC1 - - " +
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"AB4 AC2 - - Y3 AA1 Y4 AA2 - - V3 W1 V4 W2 - - - -" +
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"T3 U1 T4 R1 - R2 P3 U2 P4 -"),
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("J4p", "- M3 M4 - H3 H4 J14 AD29 - N1 N2 - J1 J2") # top to bottom, starting with 169
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]
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# Platform -----------------------------------------------------------------------------------------
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_device_map = {
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"revb" : "5CSXFC6D6F31C8ES",
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"revc" : "5CSXFC6D6F31C8ES",
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"revd" : "5CSXFC6D6F31C8",
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}
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class Platform(AlteraPlatform):
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default_clk_name = "clk50"
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default_clk_period = 1e9/50e6
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def __init__(self, revision="revd"):
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assert revision in _device_map.keys()
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self.revision = revision
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AlteraPlatform.__init__(self, _device_map[revision], _io, connectors=_connectors_hsmc_gpio_daughterboard)
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def create_programmer(self):
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return USBBlaster(cable_name="CV SoCKit")
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def do_finalize(self, fragment):
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AlteraPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
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