Florent Kermarrec 55ea71bd01 gsd_butterstick: Add initial DDR3 support. ... Validated with: ./gsd_butterstick.py --uart-name=crossover --with-etherbone --csr-csv=csr.csv --build --load litex_server --udp litex_term bridge __ _ __ _ __ / / (_) /____ | |/_/ / /__/ / __/ -_)> < /____/_/\__/\__/_/|_| Build your hardware, easily! (c) Copyright 2012-2021 Enjoy-Digital (c) Copyright 2007-2015 M-Labs BIOS built on Sep 1 2021 19:09:52 BIOS CRC passed (3d349845) Migen git sha1: 27dbf03 LiteX git sha1: 315fbe18 --=============== SoC ==================-- CPU: VexRiscv @ 75MHz BUS: WISHBONE 32-bit @ 4GiB CSR: 32-bit data ROM: 128KiB SRAM: 8KiB L2: 8KiB SDRAM: 524288KiB 16-bit @ 300MT/s (CL-6 CWL-5) --========== Initialization ============-- Initializing SDRAM @0x40000000... Switching SDRAM to software control. Read leveling: m0, b00: |01110000| delays: 02+-01 m0, b01: |00000000| delays: - m0, b02: |00000000| delays: - m0, b03: |00000000| delays: - best: m0, b00 delays: 02+-01 m1, b00: |01110000| delays: 02+-01 m1, b01: |00000000| delays: - m1, b02: |00000000| delays: - m1, b03: |00000000| delays: - best: m1, b00 delays: 02+-01 Switching SDRAM to hardware control. Memtest at 0x40000000 (2.0MiB)... Write: 0x40000000-0x40200000 2.0MiB Read: 0x40000000-0x40200000 2.0MiB Memtest OK Memspeed at 0x40000000 (Sequential, 2.0MiB)... Write speed: 13.6MiB/s Read speed: 15.6MiB/s --============== Boot ==================-- Booting from serial... Press Q or ESC to abort boot completely. sL5DdSMmkekro Timeout No boot medium found --============= Console ================-- litex>		2021-09-01 19:21:16 +02:00
..
platforms	gsd_butterstick: Add initial DDR3 support.	2021-09-01 19:21:16 +02:00
prog	Add intial ButterStick support (with just Clk, Buttons and Leds).	2021-09-01 17:33:54 +02:00
targets	gsd_butterstick: Add initial DDR3 support.	2021-09-01 19:21:16 +02:00
tools
__init__.py	beaglewire: Rename to quertyembedded_beaglewire.	2021-09-01 09:36:09 +02:00