litex-boards/litex_boards
Florent Kermarrec 57a9970257 xilinx_zc706: ADD DDR3 support in target and update/fix IOs definition in platform (Untested on hardware).
- Use/Mimic IO standards from KC705.
- Keep it to single rank for now (but add dual rank IOs in comments).
- Add DCI cascade property.
- Add sys4x and idelay clocking.
- Add LiteDRAM PHY/Core support.
2024-03-27 08:51:30 +01:00
..
platforms xilinx_zc706: ADD DDR3 support in target and update/fix IOs definition in platform (Untested on hardware). 2024-03-27 08:51:30 +01:00
prog xilinx_zc706: new Xilinx/AMD Zynq7000 based board 2024-03-26 20:49:54 +01:00
targets xilinx_zc706: ADD DDR3 support in target and update/fix IOs definition in platform (Untested on hardware). 2024-03-27 08:51:30 +01:00
__init__.py litex_boards: Remove short imports since not really longer useful and mess up Python imports. 2022-05-03 17:53:57 +02:00