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__init__.py
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Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
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2020-02-03 09:36:30 +01:00 |
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ac701.py
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targets: switch to add_ethernet method instead of EthernetSoC.
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2020-03-21 18:29:52 +01:00 |
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aller.py
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targets/PCIe: add PCIe software reset.
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2020-04-20 12:30:09 +02:00 |
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arty.py
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targets: switch to add_etherbone method.
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2020-03-21 21:40:45 +01:00 |
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arty_s7.py
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arty_s7: fix copyrights, rename to arty_s7, various minor changes to make it similar to others targets.
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2020-04-13 15:20:36 +02:00 |
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c10lprefkit.py
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targets/c10lprefkit: use Cyclone10LPPLL, remove 50MHz limitation.
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2020-04-08 08:34:59 +02:00 |
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camlink_4k.py
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targets: manual define of the SDRAM PHY is no longer needed.
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2020-04-16 11:25:59 +02:00 |
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colorlight_5a_75b.py
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targets: rename usb_cdc to usb_acm.
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2020-04-30 21:48:10 +02:00 |
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de0nano.py
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targets: use DDROutput on sdram_clock and similar configuration for all SDRAM targets.
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2020-04-10 14:43:04 +02:00 |
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de1soc.py
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targets: use DDROutput on sdram_clock and similar configuration for all SDRAM targets.
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2020-04-10 14:43:04 +02:00 |
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de2_115.py
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targets: use DDROutput on sdram_clock and similar configuration for all SDRAM targets.
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2020-04-10 14:43:04 +02:00 |
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de10lite.py
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targets: use DDROutput on sdram_clock and similar configuration for all SDRAM targets.
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2020-04-10 14:43:04 +02:00 |
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de10nano.py
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targets: use DDROutput on sdram_clock and similar configuration for all SDRAM targets.
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2020-04-10 14:43:04 +02:00 |
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ecp5_evn.py
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targets/ecp5: make sure all BaseSoC/EthernetSoc default to trellis.
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2020-03-05 10:57:59 +01:00 |
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ecpix5.py
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ecpix5: add ethernet.
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2020-04-22 20:21:59 +02:00 |
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fomu.py
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Changed wrong imports for fomu board.
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2020-02-12 12:40:07 +01:00 |
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genesys2.py
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targets: switch to add_etherbone method.
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2020-03-21 21:40:45 +01:00 |
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hadbadge.py
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targets: use DDROutput on sdram_clock and similar configuration for all SDRAM targets.
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2020-04-10 14:43:04 +02:00 |
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icebreaker.py
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targets/icebreaker: use simplified version closer to the others targets.
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2020-03-13 09:43:43 +01:00 |
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kc705.py
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targets/kc705: manual DDRPHY_CMD_DELAY adjustment no longer needed.
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2020-04-25 11:08:05 +02:00 |
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kcu105.py
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targets/kcu105: use cmd_latency=1.
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2020-04-25 12:13:49 +02:00 |
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kx2.py
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targets: switch to SoCCore/add_sdram instead of SoCSDRAM.
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2020-03-21 12:43:39 +01:00 |
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linsn_rv901t.py
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targets: use DDROutput on sdram_clock and similar configuration for all SDRAM targets.
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2020-04-10 14:43:04 +02:00 |
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mercury_xu5.py
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targets: manual define of the SDRAM PHY is no longer needed.
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2020-04-16 11:25:59 +02:00 |
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mimas_a7.py
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targets: switch to add_ethernet method instead of EthernetSoC.
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2020-03-21 18:29:52 +01:00 |
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minispartan6.py
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targets: use DDROutput on sdram_clock and similar configuration for all SDRAM targets.
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2020-04-10 14:43:04 +02:00 |
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nereid.py
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targets/PCIe: add PCIe software reset.
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2020-04-20 12:30:09 +02:00 |
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netv2.py
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targets: switch to add_ethernet method instead of EthernetSoC.
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2020-03-21 18:29:52 +01:00 |
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nexys4ddr.py
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targets: switch to add_ethernet method instead of EthernetSoC.
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2020-03-21 18:29:52 +01:00 |
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nexys_video.py
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targets: switch to add_ethernet method instead of EthernetSoC.
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2020-03-21 18:29:52 +01:00 |
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orangecrab.py
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targets: rename usb_cdc to usb_acm.
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2020-04-30 21:48:10 +02:00 |
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pipistrello.py
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targets: switch to SoCCore/add_sdram instead of SoCSDRAM.
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2020-03-21 12:43:39 +01:00 |
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simple.py
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targets/simple: use CRG from litex.build.
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2020-04-10 10:26:19 +02:00 |
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tagus.py
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targets/PCIe: add PCIe software reset.
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2020-04-20 12:30:09 +02:00 |
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trellisboard.py
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targets: manual define of the SDRAM PHY is no longer needed.
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2020-04-16 11:25:59 +02:00 |
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ulx3s.py
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targets: rename usb_cdc to usb_acm.
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2020-04-30 21:48:10 +02:00 |
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vc707.py
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targets: switch to SoCCore/add_sdram instead of SoCSDRAM.
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2020-03-21 12:43:39 +01:00 |
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vcu118.py
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targets: manual define of the SDRAM PHY is no longer needed.
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2020-04-16 11:25:59 +02:00 |
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versa_ecp5.py
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targets: manual define of the SDRAM PHY is no longer needed.
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2020-04-16 11:25:59 +02:00 |
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zcu104.py
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targets: manual define of the SDRAM PHY is no longer needed.
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2020-04-16 11:25:59 +02:00 |
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