123 lines
4.9 KiB
Python
Executable File
123 lines
4.9 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Miodrag Milanovic <mmicko@gmail.com>
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# Copyright (c) 2021 Franck Jullien <franck.jullien@collshade.fr>
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# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.gen import *
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from litex_boards.platforms import efinix_trion_t20_bga256_dev_kit
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from litex.build.io import ClkOutput
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from litex.build.generic_platform import *
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.gen.genlib.misc import WaitTimer
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from litedram.modules import NDS36PT5
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from litedram.phy import GENSDRPHY
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_sys_ps = ClockDomain()
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# # #
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# Clk/Rst.
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clk50 = platform.request("clk50")
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rst_n = platform.request("user_btn", 0)
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# A pulse is necessary to do a reset.
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self.rst_pulse = Signal()
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reset_timer = WaitTimer(25e-6*sys_clk_freq)
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self.comb += self.rst_pulse.eq(self.rst ^ reset_timer.done)
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self.comb += reset_timer.wait.eq(self.rst)
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# PLL.
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self.pll = pll = TRIONPLL(platform)
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self.comb += pll.reset.eq(~rst_n | self.rst_pulse)
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pll.register_clkin(clk50, 50e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True)
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=180, name="sdram_clk")
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=100e6, with_spi_flash=False, with_led_chaser=True, **kwargs):
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platform = efinix_trion_t20_bga256_dev_kit.Platform()
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Efinix Trion T20 BGA256 Dev Kit", **kwargs)
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# SDR SDRAM --------------------------------------------------------------------------------
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if not self.integrated_main_ram_size and sys_clk_freq <= 50e6 :
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self.specials += ClkOutput("sdram_clk", platform.request("sdram_clock"))
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self.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.sdrphy,
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module = NDS36PT5(sys_clk_freq, "1:1"),
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l2_cache_size = kwargs.get("l2_size", 8192),
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with_bist = kwargs.get("with_bist", False)
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)
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# SPI Flash --------------------------------------------------------------------------------
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if with_spi_flash:
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from litespi.modules import W25Q32JV
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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self.add_spi_flash(mode="1x", module=W25Q32JV(Codes.READ_1_1_1), with_master=True)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=efinix_trion_t20_bga256_dev_kit.Platform, description="LiteX SoC on Efinix Trion T20 BGA256 Dev Kit.")
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parser.add_target_argument("--flash", action="store_true", help="Flash bitstream.")
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parser.add_target_argument("--sys-clk-freq", default=45e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = args.sys_clk_freq,
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with_spi_flash = args.with_spi_flash,
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**parser.soc_argdict)
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if args.flash:
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from litex.build.openfpgaloader import OpenFPGALoader
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prog = OpenFPGALoader("trion_t120_bga576")
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prog.flash(0, builder.get_bitstream_filename(mode="flash", ext=".hex")) # FIXME
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if __name__ == "__main__":
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main()
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