litex-boards/litex_boards/targets
Sergiu Mosanu 7a738245af fix bitstream problem 2021-01-14 21:53:25 -05:00
..
__init__.py Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets. 2020-02-03 09:36:30 +01:00
ac701.py targets/ac701: rename --ethernet-phy to --eth-phy for consistency with others targets. 2021-01-08 18:50:01 +01:00
acorn_cle_215.py targets/xilinx: add comment on sys_clk to pll.clkin false path. 2021-01-07 08:01:54 +01:00
aller.py targets/xilinx: add comment on sys_clk to pll.clkin false path. 2021-01-07 08:01:54 +01:00
alveo_u250.py targets/xilinx: add comment on sys_clk to pll.clkin false path. 2021-01-07 08:01:54 +01:00
alveo_u280.py fix bitstream problem 2021-01-14 21:53:25 -05:00
arty.py add etherbone ip address option for relevant boards 2021-01-08 18:44:31 +01:00
arty_s7.py targets/xilinx: add comment on sys_clk to pll.clkin false path. 2021-01-07 08:01:54 +01:00
c10lprefkit.py targets/c10lprefkit: fix default sys-clk-freq. 2021-01-12 16:15:52 +01:00
camlink_4k.py targets: add --sys-clk-freq support to all targets. 2020-11-12 18:07:28 +01:00
colorlight_5a_75x.py targets/colorlight_5a_75x: rename etherbone-ip args to eth-ip. 2021-01-07 09:26:38 +01:00
crosslink_nx_evn.py nexus: Allow selection of toolchain 2020-11-25 09:45:25 +00:00
crosslink_nx_vip.py nexus: Allow selection of toolchain 2020-11-25 09:45:25 +00:00
de0nano.py targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl). 2021-01-04 11:38:07 +01:00
de1soc.py targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl). 2021-01-04 11:38:07 +01:00
de2_115.py targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl). 2021-01-04 11:38:07 +01:00
de10lite.py targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl). 2021-01-04 11:38:07 +01:00
de10nano.py targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl). 2021-01-04 11:38:07 +01:00
ecp5_evn.py targets: cleanup, uniformize build arguments between targets. 2020-11-12 11:46:00 +01:00
ecpix5.py targets/ecpix5/eth: set rx_delay to 0ns (tested with netboot on R01). 2020-12-29 16:01:12 +01:00
fk33.py targets/xilinx: add comment on sys_clk to pll.clkin false path. 2021-01-07 08:01:54 +01:00
fomu.py targets/fomu: modification to ValentyUSB no longer required. 2020-11-27 19:40:45 +01:00
genesys2.py Merge pull request #144 from gsomlo/gls-genesys2-sdcard 2021-01-07 08:12:24 +01:00
hadbadge.py targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl). 2021-01-04 11:38:07 +01:00
icebreaker.py targets: add --sys-clk-freq support to all targets. 2020-11-12 18:07:28 +01:00
kc705.py targets/xilinx: add comment on sys_clk to pll.clkin false path. 2021-01-07 08:01:54 +01:00
kcu105.py add etherbone ip address option for relevant boards 2021-01-08 18:44:31 +01:00
kx2.py targets/xilinx: add comment on sys_clk to pll.clkin false path. 2021-01-07 08:01:54 +01:00
linsn_rv901t.py targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl). 2021-01-04 11:38:07 +01:00
litefury.py targets/xilinx: add comment on sys_clk to pll.clkin false path. 2021-01-07 08:01:54 +01:00
logicbone.py target/usb_acm: switch git clone to litex-hub/valentyusb repo (up to date with LiteX). 2020-11-27 18:53:45 +01:00
mercury_xu5.py targets/xilinx: add comment on sys_clk to pll.clkin false path. 2021-01-07 08:01:54 +01:00
mimas_a7.py targets/xilinx: add comment on sys_clk to pll.clkin false path. 2021-01-07 08:01:54 +01:00
minispartan6.py targets/xilinx: add comment on sys_clk to pll.clkin false path. 2021-01-07 08:01:54 +01:00
mist.py targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl). 2021-01-04 11:38:07 +01:00
nereid.py targets/xilinx: add comment on sys_clk to pll.clkin false path. 2021-01-07 08:01:54 +01:00
netv2.py targets/xilinx: add comment on sys_clk to pll.clkin false path. 2021-01-07 08:01:54 +01:00
nexys4ddr.py targets/xilinx: add comment on sys_clk to pll.clkin false path. 2021-01-07 08:01:54 +01:00
nexys_video.py targets/xilinx: add comment on sys_clk to pll.clkin false path. 2021-01-07 08:01:54 +01:00
orangecrab.py targets/orangecrab: use new ECP5DDRPHY's cmd_delay to add extra delay on DDR3's Clock/Commands. 2021-01-12 18:57:22 +01:00
pano_logic_g2.py add etherbone ip address option for relevant boards 2021-01-08 18:44:31 +01:00
pipistrello.py targets: add --sys-clk-freq support to all targets. 2020-11-12 18:07:28 +01:00
qmtech_ep4ce15.py targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl). 2021-01-04 11:38:07 +01:00
qmtech_wukong.py add etherbone ip address option for relevant boards 2021-01-08 18:44:31 +01:00
redpitaya.py targets/xilinx: add comment on sys_clk to pll.clkin false path. 2021-01-07 08:01:54 +01:00
sds1104xe.py sds1104xe: defaults to Crossover UART. 2021-01-08 19:00:41 +01:00
simple.py targets/simple: add try/except on leds. 2020-11-12 14:26:00 +01:00
tagus.py targets/xilinx: add comment on sys_clk to pll.clkin false path. 2021-01-07 08:01:54 +01:00
tec0117.py targets: add --sys-clk-freq support to all targets. 2020-11-12 18:07:28 +01:00
tinyfpga_bx.py targets: add --sys-clk-freq support to all targets. 2020-11-12 18:07:28 +01:00
trellisboard.py targets: add --sys-clk-freq support to all targets. 2020-11-12 18:07:28 +01:00
ulx3s.py targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl). 2021-01-04 11:38:07 +01:00
vc707.py targets/xilinx: add comment on sys_clk to pll.clkin false path. 2021-01-07 08:01:54 +01:00
vcu118.py targets/xilinx: add comment on sys_clk to pll.clkin false path. 2021-01-07 08:01:54 +01:00
versa_ecp5.py add etherbone ip address option for relevant boards 2021-01-08 18:44:31 +01:00
xcu1525.py targets/xilinx: add comment on sys_clk to pll.clkin false path. 2021-01-07 08:01:54 +01:00
zcu104.py targets/xilinx: add comment on sys_clk to pll.clkin false path. 2021-01-07 08:01:54 +01:00
zybo_z7.py targets/xilinx: add comment on sys_clk to pll.clkin false path. 2021-01-07 08:01:54 +01:00