134 lines
4.5 KiB
Python
Executable File
134 lines
4.5 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2014-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2013-2014 Sebastien Bourdeauducq <sb@m-labs.hk>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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import importlib
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from migen import *
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from litex.build.io import CRG
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex_boards.platforms import tec0117
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kB = 1024
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mB = 1024*kB
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class BaseSoC(SoCCore):
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mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
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def __init__(self, bios_flash_offset, sys_clk_freq=int(12e6), **kwargs):
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platform = tec0117.Platform()
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# SoC can have littel a bram, as a treat
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kwargs["integrated_sram_size"] = 2048*2
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kwargs["integrated_rom_size"] = 0
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# Set CPU variant / reset address
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kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on TEC0117",
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ident_version = True,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = CRG(
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platform.request(platform.default_clk_name),
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~platform.request('rst'),
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)
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# SPI Flash --------------------------------------------------------------------------------
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self.add_spi_flash(mode="1x", dummy_cycles=8)
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# Add ROM linker region --------------------------------------------------------------------
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self.bus.add_region("rom", SoCRegion(
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origin = self.mem_map["spiflash"] + bios_flash_offset,
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size = 8*mB,
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linker = True)
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)
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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self.add_csr("leds")
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# Flash --------------------------------------------------------------------------------------------
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def flash(offset, path):
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from spiflash.serialflash import SerialFlashManager
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platform = tec0117.Platform()
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flash = platform.request("spiflash", 0)
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bus = platform.request("spiflash", 1)
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module = Module()
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module.comb += [
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flash.clk.eq(bus.clk),
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flash.cs_n.eq(bus.cs_n),
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flash.mosi.eq(bus.mosi),
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bus.miso.eq(flash.miso),
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]
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platform.build(module)
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prog = platform.create_programmer()
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prog.load_bitstream('build/impl/pnr/project.fs')
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dev = SerialFlashManager.get_flash_device("ftdi://ftdi:2232/2")
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dev.TIMINGS['chip'] = (4, 60) # chip is too slow
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print("Erasing flash...")
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dev.erase(0, -1)
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with open(path, 'rb') as f:
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bios = f.read()
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print("Programming flash...")
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dev.write(offset, bios)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on iCEBreaker")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--bios-flash-offset", default=0x00000, help="BIOS offset in SPI Flash (0x00000 default)")
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parser.add_argument("--flash", action="store_true", help="Flash BIOS")
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parser.add_argument("--sys-clk-freq", default=12e6, help="System clock frequency (default: 12MHz)")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc= BaseSoC(
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bios_flash_offset = args.bios_flash_offset,
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sys_clk_freq = int(float(args.sys_clk_freq)),
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.flash:
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flash(
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args.bios_flash_offset,
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os.path.join(builder.software_dir, "bios", "bios.bin"))
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(
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os.path.join(builder.gateware_dir, "impl", "pnr", "project.fs"),
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args.flash)
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if __name__ == "__main__":
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main()
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