Hardware/litex-boards
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litex-boards/litex_boards
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Florent Kermarrec 5e5ae880a4 targets/litex_acorn_baseboard: Integrate WS2812/NeoPixel. 
Tested with:
./litex_acorn_baseboard.py --cpu-type=None --uart-name=uartbone --with-ws2812 --build --csr-csv=csr.csv --load
litex_server --uart --uart-port=/dev/ttyUSBX
And test script: https://gist.github.com/enjoy-digital/c32c679a9ee4429d7f38a5ca5016a45a
2021-11-04 16:36:25 +01:00
..
platforms Merge pull request #283 from yetifrisstlama/master 2021-11-04 15:20:11 +01:00
prog prog/openocd_butterstick: Set _CHIPNAME to ecp5 (for jtag_uart/jtag_bone). 2021-10-27 17:27:07 +02:00
targets targets/litex_acorn_baseboard: Integrate WS2812/NeoPixel. 2021-11-04 16:36:25 +01:00
tools
__init__.py Add initial RZ-EasyFPGA support! (#270) 2021-09-21 09:55:22 +02:00