146 lines
5.0 KiB
Python
146 lines
5.0 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Icenowy Zheng <icenowy@aosc.io>
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# Copyright (c) 2015 Yann Sionneau <yann.sionneau@gmail.com>
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# Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
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from litex.build.openocd import OpenOCD
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk200", 0,
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Subsignal("p", Pins("E5"), IOStandard("LVDS_25")),
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Subsignal("n", Pins("D5"), IOStandard("LVDS_25")),
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),
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# Leds
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("user_led", 0, Pins("A22"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("C22"), IOStandard("LVCMOS33")),
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# Switches
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("sw", 0, Pins("C23"), IOStandard("LVCMOS33")),
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("sw", 1, Pins("B25"), IOStandard("LVCMOS33")),
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("sw", 2, Pins("A25"), IOStandard("LVCMOS33")),
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("sw", 3, Pins("A23"), IOStandard("LVCMOS33")),
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# Serial
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("serial", 0,
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Subsignal("tx", Pins("G24")),
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Subsignal("rx", Pins("F24")),
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IOStandard("LVCMOS33")
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),
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# SPIFlash
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("spiflash", 0,
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Subsignal("cs_n", Pins("P18")),
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Subsignal("clk", Pins("H13")),
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Subsignal("mosi", Pins("R14")),
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Subsignal("miso", Pins("R15")),
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Subsignal("wp", Pins("P14")),
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Subsignal("hold", Pins("N14")),
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IOStandard("LVCMOS33"),
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),
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("spiflash4x", 0,
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Subsignal("cs_n", Pins("P18")),
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Subsignal("clk", Pins("H13")),
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Subsignal("dq", Pins("R14 R15 P14 N14")),
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IOStandard("LVCMOS33")
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),
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# DDR3 SDRAM
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("ddram", 0,
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Subsignal("a", Pins(
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"D4 D3 C2 E3 B2 A2 A5 A4 B5 C3",
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"F2 A3 D1 C4 B4"),
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IOStandard("SSTL15")),
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Subsignal("ba", Pins("G4 F4 F3"), IOStandard("SSTL15")),
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Subsignal("ras_n", Pins("G2"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("G1"), IOStandard("SSTL15")),
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Subsignal("we_n", Pins("E2"), IOStandard("SSTL15")),
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Subsignal("cs_n", Pins("E1"), IOStandard("SSTL15")),
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Subsignal("dm", Pins(
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"U2 T5",
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"L7 K1"
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), IOStandard("SSTL15")),
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Subsignal("dq", Pins(
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"T2 T4 R2 P4 P3 N4 R3 T3",
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"P8 R6 T8 R5 R8 P6 T7 R7",
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"L5 M7 K3 N6 J3 N7 K5 M6",
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"L3 L2 K2 H2 M2 H1 N3 J1"
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),
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IOStandard("SSTL15"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("dqs_p", Pins(
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"R1 U6",
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"M4 N1"
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),
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IOStandard("DIFF_SSTL15"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("dqs_n", Pins(
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"P1 U5",
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"L4 M1"
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),
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IOStandard("DIFF_SSTL15"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("clk_p", Pins("C1"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_n", Pins("B1"), IOStandard("DIFF_SSTL15")),
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Subsignal("cke", Pins("J4"), IOStandard("SSTL15")),
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Subsignal("odt", Pins("H4"), IOStandard("SSTL15")),
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Subsignal("reset_n", Pins("N2"), IOStandard("SSTL15")),
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Misc("SLEW=FAST"),
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),
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## sdcard connector
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("spisdcard", 0,
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Subsignal("clk", Pins("P24")),
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Subsignal("mosi", Pins("R25"), Misc("PULLUP True")),
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Subsignal("cs_n", Pins("P25"), Misc("PULLUP True")),
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Subsignal("miso", Pins("N23"), Misc("PULLUP True")),
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Misc("SLEW=FAST"),
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IOStandard("LVCMOS33"),
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),
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("sdcard", 0,
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Subsignal("data", Pins("N23 M25 N26 P25"), Misc("PULLUP True")),
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Subsignal("cmd", Pins("R25"), Misc("PULLUP True")),
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Subsignal("clk", Pins("P24")),
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Subsignal("cd", Pins("M26"), Misc("PULLUP True")),
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Misc("SLEW=FAST"),
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IOStandard("LVCMOS33"),
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = []
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk200"
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default_clk_period = 1e9/200e6
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def __init__(self, toolchain="vivado"):
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XilinxPlatform.__init__(self, "xc7a100tfgg676-2", _io, _connectors, toolchain=toolchain)
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self.toolchain.bitstream_commands = \
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["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 1 [current_design]"]
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self.toolchain.additional_commands = \
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["write_cfgmem -force -format bin -interface spix1 -size 16 "
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"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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def create_programmer(self, name='vivado'):
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if name == 'vivado':
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return VivadoProgrammer()
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elif name == 'openocd':
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bscan_spi = "bscan_spi_xc7a100t.bit"
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return OpenOCD("openocd_xc7_ft2232.cfg", bscan_spi)
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk200:p", loose=True), 1e9/200e6)
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