108 lines
4.0 KiB
Python
Executable File
108 lines
4.0 KiB
Python
Executable File
#!/usr/bin/env python3
|
|
|
|
# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
|
|
# License: BSD
|
|
|
|
import argparse
|
|
import sys
|
|
|
|
from migen import *
|
|
from migen.genlib.resetsync import AsyncResetSynchronizer
|
|
|
|
from litex_boards.platforms import camlink_4k
|
|
|
|
from litex.soc.cores.clock import *
|
|
from litex.soc.integration.soc_sdram import *
|
|
from litex.soc.integration.builder import *
|
|
|
|
from litedram.modules import MT41K64M16
|
|
from litedram.phy import ECP5DDRPHY
|
|
|
|
# CRG ----------------------------------------------------------------------------------------------
|
|
|
|
class _CRG(Module):
|
|
def __init__(self, platform, sys_clk_freq):
|
|
self.clock_domains.cd_init = ClockDomain()
|
|
self.clock_domains.cd_por = ClockDomain(reset_less=True)
|
|
self.clock_domains.cd_sys = ClockDomain()
|
|
self.clock_domains.cd_sys2x = ClockDomain()
|
|
self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
|
|
|
|
# # #
|
|
|
|
self.stop = Signal()
|
|
|
|
# clk / rst
|
|
clk27 = platform.request("clk27")
|
|
platform.add_period_constraint(clk27, 1e9/27e6)
|
|
|
|
# power on reset
|
|
por_count = Signal(16, reset=2**16-1)
|
|
por_done = Signal()
|
|
self.comb += self.cd_por.clk.eq(ClockSignal())
|
|
self.comb += por_done.eq(por_count == 0)
|
|
self.sync.por += If(~por_done, por_count.eq(por_count - 1))
|
|
|
|
# pll
|
|
self.submodules.pll = pll = ECP5PLL()
|
|
pll.register_clkin(clk27, 27e6)
|
|
pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
|
|
pll.create_clkout(self.cd_init, 27e6)
|
|
self.specials += [
|
|
Instance("ECLKSYNCB",
|
|
i_ECLKI = self.cd_sys2x_i.clk,
|
|
i_STOP = self.stop,
|
|
o_ECLKO = self.cd_sys2x.clk),
|
|
Instance("CLKDIVF",
|
|
p_DIV = "2.0",
|
|
i_ALIGNWD = 0,
|
|
i_CLKI = self.cd_sys2x.clk,
|
|
i_RST = self.cd_sys2x.rst,
|
|
o_CDIVX = self.cd_sys.clk),
|
|
AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked),
|
|
AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked)
|
|
]
|
|
|
|
# BaseSoC ------------------------------------------------------------------------------------------
|
|
|
|
class BaseSoC(SoCSDRAM):
|
|
def __init__(self, toolchain="diamond", **kwargs):
|
|
platform = camlink_4k.Platform(toolchain=toolchain)
|
|
sys_clk_freq = int(81e6)
|
|
|
|
# SoCSDRAM ---------------------------------------------------------------------------------
|
|
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
|
|
|
|
# CRG --------------------------------------------------------------------------------------
|
|
self.submodules.crg = _CRG(platform, sys_clk_freq)
|
|
|
|
# DDR3 SDRAM -------------------------------------------------------------------------------
|
|
if not self.integrated_main_ram_size:
|
|
self.submodules.ddrphy = ECP5DDRPHY(
|
|
platform.request("ddram"),
|
|
sys_clk_freq=sys_clk_freq)
|
|
self.add_csr("ddrphy")
|
|
self.add_constant("ECP5DDRPHY", None)
|
|
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
|
|
sdram_module = MT41K64M16(sys_clk_freq, "1:2")
|
|
self.register_sdram(self.ddrphy,
|
|
geom_settings = sdram_module.geom_settings,
|
|
timing_settings = sdram_module.timing_settings)
|
|
|
|
# Build --------------------------------------------------------------------------------------------
|
|
|
|
def main():
|
|
parser = argparse.ArgumentParser(description="LiteX SoC on Cam Link 4K")
|
|
parser.add_argument("--gateware-toolchain", dest="toolchain", default="diamond",
|
|
help='gateware toolchain to use, diamond (default) or trellis')
|
|
builder_args(parser)
|
|
soc_sdram_args(parser)
|
|
args = parser.parse_args()
|
|
|
|
soc = BaseSoC(toolchain=args.toolchain, **soc_sdram_argdict(args))
|
|
builder = Builder(soc, **builder_argdict(args))
|
|
builder.build(toolchain_path="/usr/local/diamond/3.10_x64/bin/lin64")
|
|
|
|
if __name__ == "__main__":
|
|
main()
|