130 lines
4.9 KiB
Python
130 lines
4.9 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Nathaniel Lewis <github@nrlewis.dev>
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# SPDX-License-Identifier: BSD-2-Clause
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# The Alchitry Au is the "gold" standard for FPGA development boards.
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#
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# The larger of the twin successors to the Mojo V3, this board is produced
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# by SparkFun - https://www.sparkfun.com/products/16527.
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform
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from litex.build.openocd import OpenOCD
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk100", 0, Pins("N14"), IOStandard("LVCMOS33")),
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("cpu_reset", 0, Pins("P6"), IOStandard("LVCMOS33")),
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# Leds
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("user_led", 0, Pins("K13"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("K12"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("L14"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("L13"), IOStandard("LVCMOS33")),
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("user_led", 4, Pins("M16"), IOStandard("LVCMOS33")),
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("user_led", 5, Pins("M14"), IOStandard("LVCMOS33")),
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("user_led", 6, Pins("M12"), IOStandard("LVCMOS33")),
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("user_led", 7, Pins("N16"), IOStandard("LVCMOS33")),
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# Serial
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("serial", 0,
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Subsignal("tx", Pins("P16")),
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Subsignal("rx", Pins("P15")),
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IOStandard("LVCMOS33")
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),
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# I2C
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("i2c", 0,
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Subsignal("scl", Pins("E6")),
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Subsignal("sda", Pins("K5")),
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IOStandard("LVCMOS33"),
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),
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# SPIFlash
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("spiflash", 0, # clock needs to be accessed through STARTUPE2
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Subsignal("cs_n", Pins("L12")),
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Subsignal("mosi", Pins("J13")),
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Subsignal("miso", Pins("J14")),
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Subsignal("wp", Pins("K15")),
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Subsignal("hold", Pins("K16")),
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IOStandard("LVCMOS33")
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),
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("spiflash4x", 0, # clock needs to be accessed through STARTUPE2
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Subsignal("cs_n", Pins("L12")),
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Subsignal("dq", Pins("J13", "J14", "K15", "K16")),
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IOStandard("LVCMOS33")
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),
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# DDR3 SDRAM
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("ddram", 0,
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Subsignal("a", Pins(
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"F12 G16 G15 E16 H11 G12 H16",
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"H12 J16 H13 E12 H14 F13 J15"),
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IOStandard("SSTL135")),
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Subsignal("ba", Pins("E13 F15 E15"), IOStandard("SSTL135")),
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Subsignal("ras_n", Pins("D11"), IOStandard("SSTL135")),
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Subsignal("cas_n", Pins("D14"), IOStandard("SSTL135")),
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Subsignal("we_n", Pins("E11"), IOStandard("SSTL135")),
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Subsignal("dm", Pins("A14 C9"), IOStandard("SSTL135")),
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Subsignal("dq", Pins(
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"A13 B16 B14 C11 C13 C16 C12 C14",
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"D8 B11 C8 B10 A12 A8 B12 A9"),
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IOStandard("SSTL135"),
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Misc("IN_TERM=UNTUNED_SPLIT_50")),
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Subsignal("dqs_p",
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Pins("B15 B9"),
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IOStandard("DIFF_SSTL135"),
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Misc("IN_TERM=UNTUNED_SPLIT_50")),
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Subsignal("dqs_n",
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Pins("A15 A10"),
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IOStandard("DIFF_SSTL135"),
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Misc("IN_TERM=UNTUNED_SPLIT_50")),
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Subsignal("clk_p", Pins("G14"), IOStandard("DIFF_SSTL135")),
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Subsignal("clk_n", Pins("F14"), IOStandard("DIFF_SSTL135")),
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Subsignal("cke", Pins("D15"), IOStandard("SSTL135")),
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Subsignal("odt", Pins("G11"), IOStandard("SSTL135")),
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Subsignal("cs_n", Pins("D16"), IOStandard("SSTL135")),
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Subsignal("reset_n", Pins("D13"), IOStandard("SSTL135")),
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Misc("SLEW=FAST"),
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk100"
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default_clk_period = 1e9/100e6
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def __init__(self, variant="au"):
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device = {
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"au": "xc7a35t-ftg256-1",
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"au+": "xc7a100t-ftg256-2",
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}[variant]
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XilinxPlatform.__init__(self, device, _io, toolchain="vivado")
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self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 15]")
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self.toolchain.bitstream_commands = [
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"set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]",
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"set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]",
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"set_property CONFIG_VOLTAGE 3.3 [current_design]",
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"set_property CFGBVS VCCO [current_design]",
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"set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR NO [current_design]",
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"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 1 [current_design]",
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"set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]",
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]
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self.toolchain.additional_commands = \
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["write_cfgmem -force -format bin -interface spix1 -size 4 "
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"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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def create_programmer(self):
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return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a35t.bit")
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
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