173 lines
7.1 KiB
Python
Executable File
173 lines
7.1 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.soc.cores.clock.gowin_gw1n import GW1NPLL
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.video import *
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from litex_boards.platforms import tang_nano_4k
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from litehyperbus.core.hyperbus import HyperRAM
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kB = 1024
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mB = 1024*kB
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, with_video_pll=False):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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# # #
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# Clk / Rst
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clk27 = platform.request("clk27")
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rst_n = platform.request("user_btn", 0)
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# PLL
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self.submodules.pll = pll = GW1NPLL(devicename=platform.devicename, device=platform.device)
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self.comb += pll.reset.eq(~rst_n)
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pll.register_clkin(clk27, 27e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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# Video PLL
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if with_video_pll:
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self.submodules.video_pll = video_pll = GW1NPLL(devicename=platform.devicename, device=platform.device)
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self.comb += video_pll.reset.eq(~rst_n)
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video_pll.register_clkin(clk27, 27e6)
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self.clock_domains.cd_hdmi = ClockDomain()
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self.clock_domains.cd_hdmi5x = ClockDomain()
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video_pll.create_clkout(self.cd_hdmi5x, 125e6)
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self.specials += Instance("CLKDIV",
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p_DIV_MODE= "5",
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i_RESETN = rst_n,
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i_HCLKIN = self.cd_hdmi5x.clk,
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o_CLKOUT = self.cd_hdmi.clk
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)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(27e6), with_hyperram=False, with_led_chaser=True, with_video_terminal=True, **kwargs):
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platform = tang_nano_4k.Platform()
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if "cpu_type" in kwargs and kwargs["cpu_type"] == "gowin_emcu":
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kwargs["with_uart"] = False # CPU has own UART
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kwargs["integrated_sram_size"] = 0 # SRAM is directly attached to CPU
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kwargs["integrated_rom_size"] = 0 # boot flash directly attached to CPU
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else:
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# Disable Integrated ROM
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kwargs["integrated_rom_size"] = 0
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on Tang Nano 4K",
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**kwargs)
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if self.cpu_type == 'vexriscv':
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assert self.cpu_variant == 'minimal', 'use --cpu-variant=minimal to fit into number of BSRAMs'
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq, with_video_pll=with_video_terminal)
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if self.cpu_type == "gowin_emcu":
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self.cpu.connect_uart(platform.request("serial"))
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self.bus.add_region("sram", SoCRegion(
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origin=self.cpu.mem_map["sram"],
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size=16 * kB)
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)
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self.bus.add_region("rom", SoCRegion(
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origin=self.cpu.mem_map["rom"],
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size=32 * kB,
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linker=True)
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)
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else:
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# SPI Flash --------------------------------------------------------------------------------
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from litespi.modules import W25Q32
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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self.add_spi_flash(mode="1x", module=W25Q32(Codes.READ_1_1_1), with_master=False)
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# Add ROM linker region --------------------------------------------------------------------
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self.bus.add_region("rom", SoCRegion(
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origin = self.bus.regions["spiflash"].origin,
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size = 32*kB,
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linker = True)
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)
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self.cpu.set_reset_address(self.bus.regions["rom"].origin)
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# HyperRAM ---------------------------------------------------------------------------------
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if with_hyperram:
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class HyperRAMPads:
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def __init__(self):
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self.clk = Signal()
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self.rst_n = platform.request("O_hpram_reset_n")
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self.dq = platform.request("IO_hpram_dq")
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self.cs_n = platform.request("O_hpram_cs_n")
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self.rwds = platform.request("IO_hpram_rwds")
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hyperram_pads = HyperRAMPads()
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self.comb += platform.request("O_hpram_ck").eq(hyperram_pads.clk)
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self.comb += platform.request("O_hpram_ck_n").eq(~hyperram_pads.clk)
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self.submodules.hyperram = HyperRAM(hyperram_pads)
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self.bus.add_slave("main_ram", slave=self.hyperram.bus, region=SoCRegion(origin=0x40000000, size=8*mB))
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# Video ------------------------------------------------------------------------------------
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if with_video_terminal:
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self.submodules.videophy = VideoHDMIPHY(platform.request("hdmi"), clock_domain="hdmi")
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self.add_video_colorbars(phy=self.videophy, timings="640x480@75Hz", clock_domain="hdmi")
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#self.add_video_terminal(phy=self.videophy, timings="640x480@75Hz", clock_domain="hdmi") # FIXME: Free up BRAMs.
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Tang Nano 4K")
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parser.add_argument("--build", action="store_true", help="Build bitstream.")
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parser.add_argument("--load", action="store_true", help="Load bitstream.")
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parser.add_argument("--flash", action="store_true", help="Flash Bitstream.")
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parser.add_argument("--sys-clk-freq",default=27e6, help="System clock frequency.")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq=int(float(args.sys_clk_freq)),
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, "impl", "pnr", "project.fs"))
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if args.flash:
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prog = soc.platform.create_programmer()
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prog.flash(0, os.path.join(builder.gateware_dir, "impl", "pnr", "project.fs"))
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prog.flash(0, os.path.join(builder.software_dir, "bios", "bios.bin"), external=True)
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if __name__ == "__main__":
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main()
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