296 lines
13 KiB
Python
Executable File
296 lines
13 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Sergiu Mosanu <sm7ed@virginia.edu>
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# Copyright (c) 2020-2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2020 Antmicro <www.antmicro.com>
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#
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# SPDX-License-Identifier: BSD-2-Clause
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import argparse, os
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.platforms import alveo_u280
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.interconnect.axi import *
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from litex.soc.interconnect.csr import *
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from litex.soc.cores.led import LedChaser
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from litedram.modules import MTA18ASF2G72PZ
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from litedram.phy import usddrphy
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from litepcie.phy.usppciephy import USPPCIEPHY
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from litepcie.software import generate_litepcie_software
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from litedram.common import *
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from litedram.frontend.axi import *
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from litescope import LiteScopeAnalyzer
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# HBM IP
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class HBMIP(Module, AutoCSR):
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"""Xilinx Virtex US+ High Bandwidth Memory 2 IP wrapper"""
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def __init__(self, platform, hbm_ip_name="hbm_0"):
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self.platform = platform
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self.hbm_name = hbm_ip_name
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self.axi = []
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self.apb = []
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self.hbm_params = {}
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self.init_done = CSRStatus()
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# # #
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class Open(Signal): pass
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# Clocks -----------------------------------------------------------------------------------
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# Ref = 100 MHz (HBM: 900 (225-900) MHz), drives internal PLL (1 per stack).
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for i in range(2):
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self.hbm_params[f"i_HBM_REF_CLK_{i:1d}"] = ClockSignal("hbm_ref")
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# APB: 100 (50-100) MHz
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for i in range(2):
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self.hbm_params[f"i_APB_{i:1d}_PCLK"] = ClockSignal("apb")
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self.hbm_params[f"i_APB_{i:1d}_PRESET_N"] = ~ResetSignal("apb")
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# AXI: 450 (225-450) MHz
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for i in range(32):
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self.hbm_params[f"i_AXI_{i:02d}_ACLK"] = ClockSignal("axi")
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self.hbm_params[f"i_AXI_{i:02d}_ARESET_N"] = ~ResetSignal("apb")
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# AXI --------------------------------------------------------------------------------------
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for i in range(32):
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axi = AXIInterface(data_width=256, address_width=33, id_width=6)
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self.axi.append(axi)
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# AW Channel.
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self.hbm_params[f"i_AXI_{i :02d}_AWADDR"] = axi.aw.addr
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self.hbm_params[f"i_AXI_{i :02d}_AWBURST"] = axi.aw.burst
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self.hbm_params[f"i_AXI_{i :02d}_AWID"] = axi.aw.id
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self.hbm_params[f"i_AXI_{i :02d}_AWLEN"] = axi.aw.len
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self.hbm_params[f"i_AXI_{i :02d}_AWSIZE"] = axi.aw.size
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self.hbm_params[f"i_AXI_{i :02d}_AWVALID"] = axi.aw.valid
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self.hbm_params[f"o_AXI_{i :02d}_AWREADY"] = axi.aw.ready
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# W Channel.
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self.hbm_params[f"i_AXI_{i:02d}_WDATA"] = axi.w.data
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self.hbm_params[f"i_AXI_{i:02d}_WLAST"] = axi.w.last
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self.hbm_params[f"i_AXI_{i:02d}_WSTRB"] = axi.w.strb
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self.hbm_params[f"i_AXI_{i:02d}_WDATA_PARITY"] = 0 # FIXME: Manage parity?
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self.hbm_params[f"i_AXI_{i:02d}_WVALID"] = axi.w.valid
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self.hbm_params[f"o_AXI_{i:02d}_WREADY"] = axi.w.ready
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# B Channel.
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self.hbm_params[f"o_AXI_{i:02d}_BID"] = axi.b.id
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self.hbm_params[f"o_AXI_{i:02d}_BRESP"] = axi.b.resp
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self.hbm_params[f"o_AXI_{i:02d}_BVALID"] = axi.b.valid
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self.hbm_params[f"i_AXI_{i:02d}_BREADY"] = axi.b.ready
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# AR Channel.
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self.hbm_params[f"i_AXI_{i:02d}_ARADDR"] = axi.ar.addr
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self.hbm_params[f"i_AXI_{i:02d}_ARBURST"] = axi.ar.burst
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self.hbm_params[f"i_AXI_{i:02d}_ARID"] = axi.ar.id
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self.hbm_params[f"i_AXI_{i:02d}_ARLEN"] = axi.ar.len
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self.hbm_params[f"i_AXI_{i:02d}_ARSIZE"] = axi.ar.size
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self.hbm_params[f"i_AXI_{i:02d}_ARVALID"] = axi.ar.valid
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self.hbm_params[f"o_AXI_{i:02d}_ARREADY"] = axi.ar.ready
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# R Channel.
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self.hbm_params[f"o_AXI_{i:02d}_RDATA_PARITY"] = Open() # FIXME: Manage parity?
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self.hbm_params[f"o_AXI_{i:02d}_RDATA"] = axi.r.data
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self.hbm_params[f"o_AXI_{i:02d}_RID"] = axi.r.id
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self.hbm_params[f"o_AXI_{i:02d}_RLAST"] = axi.r.last
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self.hbm_params[f"o_AXI_{i:02d}_RRESP"] = axi.r.resp
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self.hbm_params[f"o_AXI_{i:02d}_RVALID"] = axi.r.valid
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self.hbm_params[f"i_AXI_{i:02d}_RREADY"] = axi.r.ready
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# APB --------------------------------------------------------------------------------------
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# FIXME: Connect to CSR or Wishbone.
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apb_complete = Signal(2)
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for i in range(2):
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self.hbm_params[f"i_APB_{i:1d}_PWDATA"] = 0
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self.hbm_params[f"i_APB_{i:1d}_PADDR"] = 0
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self.hbm_params[f"i_APB_{i:1d}_PENABLE"] = 0
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self.hbm_params[f"i_APB_{i:1d}_PSEL"] = 0
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self.hbm_params[f"i_APB_{i:1d}_PWRITE"] = 0
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self.hbm_params[f"o_APB_{i:1d}_PRDATA"] = Open()
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self.hbm_params[f"o_APB_{i:1d}_PREADY"] = Open()
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self.hbm_params[f"o_APB_{i:1d}_PSLVERR"] = Open()
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self.hbm_params[f"o_apb_complete_{i:1d}"] = apb_complete[i]
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self.comb += self.init_done.status.eq(apb_complete == 0b11)
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# Temperature ------------------------------------------------------------------------------
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for i in range(2):
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self.hbm_params[f"o_DRAM_{i:1d}_STAT_CATTRIP"] = Open()
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self.hbm_params[f"o_DRAM_{i:1d}_STAT_TEMP"] = Open()
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def add_sources(self, platform):
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this_dir = os.path.dirname(os.path.abspath(os.path.realpath(__file__)))
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os.system("wget https://github.com/litex-hub/litex-boards/files/6893157/hbm_0.xci.txt")
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os.makedirs("ip/hbm", exist_ok=True)
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os.system("mv hbm_0.xci.txt ip/hbm/hbm_0.xci")
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platform.add_ip(os.path.join(this_dir, "ip", "hbm", self.hbm_name + ".xci"))
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def do_finalize(self):
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self.add_sources(self.platform)
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self.specials += Instance(self.hbm_name, **self.hbm_params)
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, ddram_channel, with_hbm):
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if with_hbm:
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_hbm_ref = ClockDomain()
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self.clock_domains.cd_apb = ClockDomain()
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else: # ddr4
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_pll4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_idelay = ClockDomain()
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# # #
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if with_hbm:
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self.submodules.pll = pll = USMMCM(speedgrade=-2)
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pll.register_clkin(platform.request("sysclk", ddram_channel), 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_hbm_ref, 100e6)
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pll.create_clkout(self.cd_apb, 100e6)
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platform.add_false_path_constraints(self.cd_sys.clk, self.cd_apb.clk)
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else: # ddr4
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self.submodules.pll = pll = USMMCM(speedgrade=-2)
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(platform.request("sysclk", ddram_channel), 100e6)
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pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
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pll.create_clkout(self.cd_idelay, 600e6) #, with_reset=False
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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self.specials += [
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Instance("BUFGCE_DIV", name="main_bufgce_div",
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p_BUFGCE_DIVIDE=4,
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i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk),
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Instance("BUFGCE", name="main_bufgce",
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i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk),
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# AsyncResetSynchronizer(self.cd_idelay, ~pll.locked),
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]
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self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_idelay, cd_sys=self.cd_sys)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(150e6), ddram_channel=0, with_pcie=False, with_led_chaser=False, with_hbm=False, **kwargs):
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platform = alveo_u280.Platform()
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if with_hbm:
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assert 225e6 <= sys_clk_freq <= 450e6
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on Alveo U280 (ES1)",
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq, ddram_channel, with_hbm)
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if with_hbm:
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# JTAGBone --------------------------------------------------------------------------------
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#self.add_jtagbone(chain=2) # Chain 1 already used by HBM2 debug probes.
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# Add HBM Core.
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self.submodules.hbm = hbm = ClockDomainsRenamer({"axi": "sys"})(HBMIP(platform))
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# Connect four of the HBM's AXI interfaces to the main bus of the SoC.
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for i in range(4):
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axi_hbm = hbm.axi[i]
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axi_lite_hbm = AXILiteInterface(data_width=256, address_width=33)
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self.submodules += AXILite2AXI(axi_lite_hbm, axi_hbm)
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self.bus.add_slave(f"hbm{i}", axi_lite_hbm, SoCRegion(origin=0x4000_0000 + 0x1000_0000*i, size=0x1000_0000)) # 256MB.
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else:
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# DDR4 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram", ddram_channel),
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memtype = "DDR4",
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cmd_latency = 1, # seems to work better with cmd_latency=1
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sys_clk_freq = sys_clk_freq,
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iodelay_clk_freq = 600e6,
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is_rdimm = True)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MTA18ASF2G72PZ(sys_clk_freq, "1:4"),
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size = 0x40000000,
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# Firmware RAM (To ease initial LiteDRAM calibration support) ------------------------------
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self.add_ram("firmware_ram", 0x20000000, 0x8000)
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# PCIe -------------------------------------------------------------------------------------
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if with_pcie:
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self.submodules.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"),
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data_width = 128,
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bar0_size = 0x20000)
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self.add_pcie(phy=self.pcie_phy, ndmas=1)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("gpio_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Alveo U280")
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parser.add_argument("--build", action="store_true", help="Build bitstream.")
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parser.add_argument("--load", action="store_true", help="Load bitstream.")
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parser.add_argument("--sys-clk-freq", default=150e6, help="System clock frequency.") # HBM2 with 250MHz, DDR4 with 150MHz (1:4)
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parser.add_argument("--ddram-channel", default="0", help="DDRAM channel (0, 1, 2 or 3).") # also selects clk 0 or 1
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parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
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parser.add_argument("--driver", action="store_true", help="Generate PCIe driver.")
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parser.add_argument("--with-hbm", action="store_true", help="Use HBM2.")
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parser.add_argument("--with-analyzer", action="store_true", help="Enable Analyzer.")
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parser.add_argument("--with-led-chaser", action="store_true", help="Enable LED Chaser.")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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if args.with_hbm:
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args.sys_clk_freq = 250e6
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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ddram_channel = int(args.ddram_channel, 0),
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with_pcie = args.with_pcie,
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with_led_chaser = args.with_led_chaser,
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with_hbm = args.with_hbm,
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with_analyzer = args.with_analyzer,
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.driver:
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generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver"))
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
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if __name__ == "__main__":
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main()
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