153 lines
6.2 KiB
Python
Executable File
153 lines
6.2 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2022 Sylvain Munaut <tnt@246tNt.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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from migen import *
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from litex_boards.platforms import adi_adrv2crr_fmc
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.clock import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.pwm import PWM
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from litex.soc.cores.xadc import ZynqUSPSystemMonitor
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from litedram.modules import MT40A512M16
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from litedram.phy import usddrphy
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from litepcie.phy.usppciephy import USPPCIEPHY
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from litepcie.software import generate_litepcie_software
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# CRG ----------------------------------------------------------------------------------------------
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class CRG(Module):
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def __init__(self, platform, sys_clk_freq, ddram_channel):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain()
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self.clock_domains.cd_pll4x = ClockDomain()
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self.clock_domains.cd_idelay = ClockDomain()
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# # #
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self.submodules.pll = pll = USPMMCM(speedgrade=-1)
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(platform.request("ddram_refclk", ddram_channel), 300e6)
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pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
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pll.create_clkout(self.cd_idelay, 400e6)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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self.specials += [
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Instance("BUFGCE_DIV", name="main_bufgce_div",
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p_BUFGCE_DIVIDE=4,
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i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk),
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Instance("BUFGCE", name="main_bufgce",
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i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk),
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]
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self.submodules.idelayctrl = USPIDELAYCTRL(cd_ref=self.cd_idelay, cd_sys=self.cd_sys)
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# BaseSoC -----------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(150e6), ddram_channel=0, with_led_chaser=True,
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with_pcie=False, **kwargs):
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platform = adi_adrv2crr_fmc.Platform()
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = CRG(platform, sys_clk_freq, ddram_channel)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on ADI ADRV2CRR-FMC", **kwargs)
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# DDR4 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = usddrphy.USPDDRPHY(
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pads = platform.request("ddram", ddram_channel),
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memtype = "DDR4",
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sys_clk_freq = sys_clk_freq,
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iodelay_clk_freq = 400e6)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT40A512M16(sys_clk_freq, "1:4"),
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size = 0x40000000,
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# PCIe -------------------------------------------------------------------------------------
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if with_pcie:
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assert self.csr_data_width == 32
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self.submodules.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"),
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speed = "gen3",
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data_width = 128,
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bar0_size = 0x20000)
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self.add_pcie(phy=self.pcie_phy, ndmas=1)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Fan --------------------------------------------------------------------------------------
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# Full speed is _really_ loud and with this demo bitstream which is almost
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# empty, we can slow it way down and still keep the FPGA < 10C above ambient
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self.submodules.fan = PWM(
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default_enable = 1,
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default_period = 2500,
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default_width = 500
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)
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self.comb += platform.request("fan").pwm_n.eq(~self.fan.pwm)
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# SYSMON -----------------------------------------------------------------------------------
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self.submodules.sysmon = ZynqUSPSystemMonitor()
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# JTAG -------------------------------------------------------------------------------------
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self.add_jtagbone()
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXSoCArgumentParser(description="LiteX SoC on ADI ADRV2CRR-FMC")
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target_group = parser.add_argument_group(title="Target options")
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target_group.add_argument("--build", action="store_true", help="Build design")
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target_group.add_argument("--load", action="store_true", help="Load bitstream.")
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target_group.add_argument("--sys-clk-freq", default=150e6, help="System clock frequency (default: 150 MHz)")
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target_group.add_argument("--with-pcie", action="store_true", help="Enable PCIe support")
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target_group.add_argument("--driver", action="store_true", help="Generate PCIe driver")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_pcie = args.with_pcie,
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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if args.build:
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builder.build()
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if args.driver:
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generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver"))
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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main()
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