119 lines
4.8 KiB
Python
Executable File
119 lines
4.8 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2020-2021 Romain Dolbeau <romain@dolbeau.org>
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# SPDX-License-Identifier: BSD-2-Clause
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# Support for the ZTEX USB-FGPA Module 2.13:https://www.ztex.de/usb-fpga-2/usb-fpga-2.13.e.html.
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# With (no-so-optional) expansion, either the ZTEX Debug board:
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# https://www.ztex.de/usb-fpga-2/debug.e.html
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# Or the SBusFPGA adapter board:
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# https://github.com/rdolbeau/SBusFPGA
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from migen import *
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from litex.gen import LiteXModule
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from litex_boards.platforms import ztex213
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litedram.modules import MT41J128M16
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from litedram.phy import s7ddrphy
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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self.cd_sys = ClockDomain()
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self.cd_sys4x = ClockDomain()
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self.cd_sys4x_dqs = ClockDomain()
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self.cd_idelay = ClockDomain()
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self.cd_por = ClockDomain()
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# # #
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clk48 = platform.request("clk48")
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self.pll = pll = S7MMCM(speedgrade=-1)
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pll.register_clkin(clk48, 48e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_idelay, 200e6)
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# Power on reset
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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self.comb += self.cd_por.clk.eq(clk48)
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self.comb += por_done.eq(por_count == 0)
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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self.comb += pll.reset.eq(~por_done)
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self.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, variant="ztex2.13a", sys_clk_freq=100e6, expansion="debug",
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with_led_chaser = True,
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**kwargs):
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platform = ztex213.Platform(variant=variant, expansion=expansion)
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Ztex 2.13", **kwargs)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT41J128M16(sys_clk_freq, "1:4"),
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=ztex213.Platform, description="LiteX SoC on Ztex 2.13.")
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parser.add_target_argument("--expansion", default="debug", help="Expansion board (debug or sbus).")
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parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
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parser.add_target_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
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args = parser.parse_args()
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soc = BaseSoC(sys_clk_freq=args.sys_clk_freq, expansion=args.expansion, **parser.soc_argdict)
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assert not (args.with_spi_sdcard and args.with_sdcard)
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if args.with_spi_sdcard:
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soc.add_spi_sdcard() # SBus only
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if args.with_sdcard:
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soc.add_sdcard() # SBus only
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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main()
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