201 lines
7.9 KiB
Python
Executable File
201 lines
7.9 KiB
Python
Executable File
#!/usr/bin/env python3
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# This file is Copyright (c) 2018-2019 Rohit Singh <rohit@rohitksingh.in>
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# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import os
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import argparse
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import sys
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from migen import *
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from migen.genlib.misc import WaitTimer
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from litex.build import tools
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from litex_boards.platforms import aller
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from litex.soc.interconnect.csr import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litex.soc.integration.export import *
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from litex.soc.cores.clock import *
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from litex.soc.cores.dna import DNA
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from litex.soc.cores.xadc import XADC
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from litex.soc.cores.icap import ICAP
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from litex.soc.cores.led import LedChaser
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from litedram.modules import MT41J128M16
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from litedram.phy import s7ddrphy
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from litepcie.phy.s7pciephy import S7PCIEPHY
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from litepcie.core import LitePCIeEndpoint, LitePCIeMSI
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from litepcie.frontend.dma import LitePCIeDMA
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from litepcie.frontend.wishbone import LitePCIeWishboneBridge
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# CRG ----------------------------------------------------------------------------------------------
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class CRG(Module, AutoCSR):
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def __init__(self, platform, sys_clk_freq):
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self.rst = CSR()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
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self.clock_domains.cd_clk200 = ClockDomain()
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# Clk/Rst
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clk100 = platform.request("clk100")
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# Delay software reset by 10us to ensure write has been acked on PCIe.
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rst_delay = WaitTimer(int(10e-6*sys_clk_freq))
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self.submodules += rst_delay
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self.sync += If(self.rst.re, rst_delay.wait.eq(1))
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# PLL
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self.submodules.pll = pll = S7PLL()
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self.comb += pll.reset.eq(rst_delay.done)
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pll.register_clkin(clk100, 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_clk200, 200e6)
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
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# PCIeSoC -----------------------------------------------------------------------------------------
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class PCIeSoC(SoCCore):
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def __init__(self, platform, **kwargs):
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sys_clk_freq = int(100e6)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on Aller",
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ident_version = True,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = CRG(platform, sys_clk_freq)
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self.add_csr("crg")
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# DNA --------------------------------------------------------------------------------------
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self.submodules.dna = DNA()
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self.dna.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk)
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self.add_csr("dna")
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# XADC -------------------------------------------------------------------------------------
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self.submodules.xadc = XADC()
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self.add_csr("xadc")
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# ICAP -------------------------------------------------------------------------------------
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self.submodules.icap = ICAP(platform)
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self.icap.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk)
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self.add_csr("icap")
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq,
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iodelay_clk_freq = 200e6)
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self.add_csr("ddrphy")
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT41J128M16(sys_clk_freq, "1:4"),
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origin = self.mem_map["main_ram"],
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size = kwargs.get("max_sdram_size", 0x40000000),
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l2_cache_size = kwargs.get("l2_size", 8192),
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l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
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l2_cache_reverse = True
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)
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# PCIe -------------------------------------------------------------------------------------
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# PHY
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self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
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data_width = 128,
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bar0_size = 0x20000)
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self.pcie_phy.add_timing_constraints(platform)
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platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
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self.add_csr("pcie_phy")
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# Endpoint
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self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, max_pending_requests=8)
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# Wishbone bridge
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self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint,
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base_address = self.mem_map["csr"])
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self.add_wb_master(self.pcie_bridge.wishbone)
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# DMA0
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self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
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with_buffering = True, buffering_depth=1024,
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with_loopback = True)
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self.add_csr("pcie_dma0")
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# DMA1
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self.submodules.pcie_dma1 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
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with_buffering = True, buffering_depth=1024,
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with_loopback = True)
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self.add_csr("pcie_dma1")
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self.add_constant("DMA_CHANNELS", 2)
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# MSI
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self.submodules.pcie_msi = LitePCIeMSI()
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self.add_csr("pcie_msi")
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self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
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self.interrupts = {
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"PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq,
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"PCIE_DMA0_READER": self.pcie_dma0.reader.irq,
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"PCIE_DMA1_WRITER": self.pcie_dma1.writer.irq,
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"PCIE_DMA1_READER": self.pcie_dma1.reader.irq,
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}
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for i, (k, v) in enumerate(sorted(self.interrupts.items())):
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self.comb += self.pcie_msi.irqs[i].eq(v)
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self.add_constant(k + "_INTERRUPT", i)
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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pads = Cat(*[platform.request("user_led", i) for i in range(3)]),
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sys_clk_freq = sys_clk_freq)
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self.add_csr("leds")
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def generate_software_headers(self):
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csr_header = get_csr_header(self.csr_regions, self.constants, with_access_functions=False)
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tools.write_to_file("csr.h", csr_header)
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soc_header = get_soc_header(self.constants, with_access_functions=False)
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tools.write_to_file("soc.h", soc_header)
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mem_header = get_mem_header(self.mem_regions)
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tools.write_to_file("mem.h", mem_header)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Aller")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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builder_args(parser)
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soc_sdram_args(parser)
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args = parser.parse_args()
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# Enforce arguments
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args.uart_name = "crossover"
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args.csr_data_width = 32
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platform = aller.Platform()
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soc = PCIeSoC(platform, **soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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vns = builder.build(run=args.build)
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soc.generate_software_headers()
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit"))
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if __name__ == "__main__":
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main()
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