mirror of
https://github.com/litex-hub/litex-boards.git
synced 2025-01-03 03:43:36 -05:00
a611f035d6
Moving CRG simplify reset with NaxRiscv debug module and is in fact more logical. Also do some minor updates/cosmetic changes while touching CRG/SoCCore.
172 lines
7.7 KiB
Python
Executable file
172 lines
7.7 KiB
Python
Executable file
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from litex_boards.platforms import litex_acorn_baseboard
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from litex.build.lattice.trellis import trellis_args, trellis_argdict
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.video import VideoHDMIPHY
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from litex.soc.cores.bitbang import I2CMaster
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from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, with_video_pll=False):
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self.rst = Signal()
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self.clock_domains.cd_por = ClockDomain()
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self.clock_domains.cd_sys = ClockDomain()
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# # #
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# Clk / Rst
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clk50 = platform.request("clk50")
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# Power on reset
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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self.comb += self.cd_por.clk.eq(clk50)
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self.comb += por_done.eq(por_count == 0)
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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# PLL
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self.submodules.pll = pll = ECP5PLL()
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self.comb += pll.reset.eq(~por_done | self.rst)
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pll.register_clkin(clk50, 50e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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# Video PLL
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if with_video_pll:
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self.submodules.video_pll = video_pll = ECP5PLL()
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self.comb += pll.reset.eq(~por_done | self.rst)
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video_pll.register_clkin(clk50, 50e6)
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self.clock_domains.cd_hdmi = ClockDomain()
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self.clock_domains.cd_hdmi5x = ClockDomain()
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video_pll.create_clkout(self.cd_hdmi, 40e6, margin=0)
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video_pll.create_clkout(self.cd_hdmi5x, 200e6, margin=0)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(75e6),
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with_spi_flash = False,
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with_ethernet = False,
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with_etherbone = False,
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with_video_terminal = False,
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with_lcd = False,
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with_ws2812 = False,
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**kwargs):
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platform = litex_acorn_baseboard.Platform(toolchain="trellis")
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq, with_video_pll=with_video_terminal)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on LiteX M2 Baseboard", **kwargs)
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# SPI Flash --------------------------------------------------------------------------------
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if with_spi_flash:
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from litespi.modules import W25Q128JV
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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self.add_spi_flash(mode="4x", module=W25Q128JV(Codes.READ_1_1_4), with_master=True)
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# Ethernet / Etherbone ---------------------------------------------------------------------
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if with_ethernet or with_etherbone:
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self.submodules.ethphy = LiteEthPHYRGMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"),
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rx_delay = 0e-9)
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if with_ethernet:
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self.add_ethernet(phy=self.ethphy)
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if with_etherbone:
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self.add_etherbone(phy=self.ethphy)
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# Video ------------------------------------------------------------------------------------
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if with_video_terminal:
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self.submodules.videophy = VideoHDMIPHY(platform.request("hdmi"), clock_domain="hdmi", pn_swap=["g", "b"])
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self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi")
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# LCD --------------------------------------------------------------------------------------
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if with_lcd:
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self.submodules.i2c = I2CMaster(platform.request("lcd"))
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# M2 --------------------------------------------------------------------------------------
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self.comb += platform.request("m2_devslp").eq(0) # Enable SATA M2.
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# WS2812 ----------------------------------------------------------------------------------
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if with_ws2812:
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from litex.build.generic_platform import Pins, IOStandard
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.cores.led import WS2812
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platform.add_extension([("ws2812", 0, Pins("pmod1:0"), IOStandard("LVCMOS33"))])
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self.submodules.ws2812 = WS2812(platform.request("ws2812"), nleds=64, sys_clk_freq=sys_clk_freq)
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self.bus.add_slave(name="ws2812", slave=self.ws2812.bus, region=SoCRegion(
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origin = 0x2000_0000,
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size = 64*4,
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))
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXSoCArgumentParser(description="LiteX SoC on LiteX Acorn Baseboard")
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target_group = parser.add_argument_group(title="Target options")
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target_group.add_argument("--build", action="store_true", help="Build bitstream.")
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target_group.add_argument("--load", action="store_true", help="Load bitstream.")
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target_group.add_argument("--flash", action="store_true", help="Flash bitstream to SPI Flash.")
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target_group.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
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ethopts = target_group.add_mutually_exclusive_group()
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ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
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ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
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sdopts = target_group.add_mutually_exclusive_group()
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sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
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sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
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viopts = target_group.add_mutually_exclusive_group()
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viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
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target_group.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
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target_group.add_argument("--with-lcd", action="store_true", help="Enable OLED LCD support.")
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target_group.add_argument("--with-ws2812", action="store_true", help="Enable WS2812 on PMOD1:0.")
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builder_args(parser)
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soc_core_args(parser)
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trellis_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_spi_flash = args.with_spi_flash,
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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with_video_terminal = args.with_video_terminal,
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with_lcd = args.with_lcd,
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with_ws2812 = args.with_ws2812,
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**soc_core_argdict(args)
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)
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if args.with_spi_sdcard:
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soc.add_spi_sdcard()
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if args.with_sdcard:
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soc.add_sdcard()
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builder = Builder(soc, **builder_argdict(args))
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builder.build(**trellis_argdict(args), run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if args.flash:
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prog = soc.platform.create_programmer()
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prog.flash(None, prog.load_bitstream(builder.get_bitstream_filename(mode="flash")))
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if __name__ == "__main__":
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main()
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