47 lines
1.8 KiB
Python
47 lines
1.8 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2022 Ilia Sergachev <ilia@sergachev.ch>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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("clk100", 0,
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Subsignal("p", Pins("G12"), IOStandard("LVDS_25")),
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Subsignal("n", Pins("G11"), IOStandard("LVDS_25"))
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),
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("user_led", 0, Pins("C13"), IOStandard("LVCMOS18")),
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("user_led", 1, Pins("D14"), IOStandard("LVCMOS18")),
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("user_led", 2, Pins("D12"), IOStandard("LVCMOS18")),
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("user_led", 3, Pins("D13"), IOStandard("LVCMOS18")),
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("user_led", 4, Pins("AW18"), IOStandard("LVCMOS12")),
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("user_led", 5, Pins("AV18"), IOStandard("LVCMOS12")),
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("user_led", 6, Pins("BA19"), IOStandard("LVCMOS12")),
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("user_led", 7, Pins("AP21"), IOStandard("LVCMOS12")),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk100"
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default_clk_period = 1e9 / 100e6
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def __init__(self, toolchain="vivado"):
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XilinxPlatform.__init__(self, "xczu49dr-ffvf1760-2-e", _io, toolchain=toolchain)
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self.toolchain.bitstream_commands = \
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["set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]", ]
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self.default_clk_freq = 1e9 / self.default_clk_period
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def create_programmer(self):
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return VivadoProgrammer()
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def do_finalize(self, fragment, *args, **kwargs):
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XilinxPlatform.do_finalize(self, fragment, *args, **kwargs)
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self.add_period_constraint(self.lookup_request(self.default_clk_name, loose=True), self.default_clk_period)
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