mirror of
https://github.com/litex-hub/litex-boards.git
synced 2025-01-03 03:43:36 -05:00
8211aca2e8
We initially wanted to provide different level of support for the platforms/targets, mainly to avoid too much maintenance and let each contributor update its contributed platforms and targets, but it's easier to update all platforms/targets all-together when LiteX evolves or changes (and that's what has been done on litex-boards since the creation of the repository). So let just simplify things and avoid this differentiation.
75 lines
2.6 KiB
Python
75 lines
2.6 KiB
Python
# This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticePlatform
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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("clk25", 0, Pins("G2"), IOStandard("LVCMOS33")),
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("rst", 0, Pins("R1"), IOStandard("LVCMOS33")),
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("user_led", 0, Pins("B2"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("C2"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("C1"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("D2"), IOStandard("LVCMOS33")),
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("user_led", 0, Pins("D1"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("E2"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("E1"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("H3"), IOStandard("LVCMOS33")),
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("serial", 0,
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Subsignal("tx", Pins("L4"), IOStandard("LVCMOS33")),
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Subsignal("rx", Pins("M1"), IOStandard("LVCMOS33"))
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),
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("sdram_clock", 0, Pins("F19"), IOStandard("LVCMOS33")),
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("sdram", 0,
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Subsignal("a", Pins("M20 M19 L20 L19 K20 K19 K18 J20 J19 H20 N19 G20 G19")),
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Subsignal("dq", Pins("J16 L18 M18 N18 P18 T18 T17 U20 E19 D20 D19 C20 E18 F18 J18 J17")),
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Subsignal("we_n", Pins("T20")),
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Subsignal("ras_n", Pins("R20")),
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Subsignal("cas_n", Pins("T19")),
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Subsignal("cs_n", Pins("P20")),
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Subsignal("cke", Pins("F20")),
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Subsignal("ba", Pins("P19 N20")),
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Subsignal("dm", Pins("U19 E20")),
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IOStandard("LVCMOS33"), Misc("SLEWRATE=FAST")
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),
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("wifi_gpio0", 0, Pins("L2"), IOStandard("LVCMOS33")),
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("ext0p", 0, Pins("B11"), IOStandard("LVCMOS33")),
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("ext1p", 0, Pins("A10"), IOStandard("LVCMOS33")),
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("gpio", 0,
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Subsignal("p", Pins("B11")),
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Subsignal("n", Pins("C11")),
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IOStandard("LVCMOS33")
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),
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("gpio", 1,
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Subsignal("p", Pins("A10")),
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Subsignal("n", Pins("A11")),
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IOStandard("LVCMOS33")
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),
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("gpio", 2,
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Subsignal("p", Pins("A9")),
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Subsignal("n", Pins("B10")),
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IOStandard("LVCMOS33")
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),
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("gpio", 3,
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Subsignal("p", Pins("B9")),
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Subsignal("n", Pins("C10")),
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IOStandard("LVCMOS33")
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(LatticePlatform):
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default_clk_name = "clk25"
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default_clk_period = 1e9/25e6
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def __init__(self, device="LFE5U-45F", **kwargs):
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LatticePlatform.__init__(self, device + "-6BG381C", _io, **kwargs)
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