143 lines
5.6 KiB
Python
Executable File
143 lines
5.6 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Hans Baier <hansfbaier@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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# iCESugar FPGA: https://www.aliexpress.com/item/4001201771358.html
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import os
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.platforms import muselab_icesugar
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from litex.soc.cores.ram import Up5kSPRAM
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from litex.soc.cores.clock import iCE40PLL
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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kB = 1024
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mB = 1024*kB
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_por = ClockDomain(reset_less=True)
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# # #
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# Clk/Rst
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clk12 = platform.request("clk12")
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# Power On Reset
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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self.comb += self.cd_por.clk.eq(ClockSignal())
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self.comb += por_done.eq(por_count == 0)
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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# PLL
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self.submodules.pll = pll = iCE40PLL(primitive="SB_PLL40_PAD")
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(clk12, 12e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=False)
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self.specials += AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked)
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platform.add_period_constraint(self.cd_sys.clk, 1e9/sys_clk_freq)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
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def __init__(self, bios_flash_offset, sys_clk_freq=int(24e6), with_led_chaser=True,
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with_video_terminal=False, **kwargs):
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platform = muselab_icesugar.Platform()
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# Disable Integrated ROM/SRAM since too large for iCE40 and UP5K has specific SPRAM.
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kwargs["integrated_sram_size"] = 0
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kwargs["integrated_rom_size"] = 0
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# Set CPU variant / reset address
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kwargs["cpu_variant"] = "lite"
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kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on Muselab iCESugar",
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ident_version = True,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# 128KB SPRAM (used as SRAM) ---------------------------------------------------------------
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self.submodules.spram = Up5kSPRAM(size=64*kB)
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self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=64*kB))
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# SPI Flash --------------------------------------------------------------------------------
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from litespi.modules import W25Q64FV
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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self.add_spi_flash(mode="1x", module=W25Q64FV(Codes.READ_1_1_1), with_master=False)
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# Add ROM linker region --------------------------------------------------------------------
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self.bus.add_region("rom", SoCRegion(
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origin = self.mem_map["spiflash"] + bios_flash_offset,
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size = 32*kB,
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linker = True)
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)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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led_pads = platform.request_all("user_led_n")
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self.submodules.leds = LedChaser(
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pads = led_pads,
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sys_clk_freq = sys_clk_freq)
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# Flash --------------------------------------------------------------------------------------------
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def flash(bios_flash_offset):
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from litex.build.lattice.programmer import IceSugarProgrammer
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prog = IceSugarProgrammer()
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prog.flash(bios_flash_offset, "build/muselab_icesugar/software/bios/bios.bin")
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prog.flash(0x00000000, "build/muselab_icesugar/gateware/muselab_icesugar.bin")
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on iCEBreaker")
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parser.add_argument("--build", action="store_true", help="Build bitstream.")
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parser.add_argument("--load", action="store_true", help="Load bitstream.")
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parser.add_argument("--flash", action="store_true", help="Flash Bitstream.")
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parser.add_argument("--sys-clk-freq", default=24e6, help="System clock frequency.")
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parser.add_argument("--bios-flash-offset", default="0x40000", help="BIOS offset in SPI Flash.")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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bios_flash_offset = int(args.bios_flash_offset, 0),
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sys_clk_freq = int(float(args.sys_clk_freq)),
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bin"))
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if args.flash:
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flash(int(args.bios_flash_offset, 0))
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if __name__ == "__main__":
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main()
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