170 lines
7.0 KiB
Python
Executable File
170 lines
7.0 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 Gary Wong <gtw@gnu.org>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.platforms import fpc_iii
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from litex.build.lattice.trellis import trellis_args, trellis_argdict
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litedram.modules import IS43TR16256A
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from litedram.phy import ECP5DDRPHY
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from liteeth.phy.mii import LiteEthPHYMII
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.clock_domains.cd_init = ClockDomain()
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self.clock_domains.cd_por = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys2x = ClockDomain()
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self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
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self.stop = Signal()
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self.reset = Signal()
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# Clk / Rst
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clk25 = platform.request("clk25")
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# Power on reset
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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self.comb += self.cd_por.clk.eq(clk25)
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self.comb += por_done.eq(por_count == 0)
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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# PLL
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sys2x_clk_ecsout = Signal()
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self.submodules.pll = pll = ECP5PLL()
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self.comb += pll.reset.eq(~por_done | self.rst)
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pll.register_clkin(clk25, 25e6)
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pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
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pll.create_clkout(self.cd_init, 25e6)
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self.specials += [
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Instance("ECLKBRIDGECS",
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i_CLK0 = self.cd_sys2x_i.clk,
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i_SEL = 0,
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o_ECSOUT = sys2x_clk_ecsout,
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),
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Instance("ECLKSYNCB",
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i_ECLKI = sys2x_clk_ecsout,
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i_STOP = self.stop,
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o_ECLKO = self.cd_sys2x.clk),
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Instance("CLKDIVF",
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p_DIV = "2.0",
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i_ALIGNWD = 0,
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i_CLKI = self.cd_sys2x.clk,
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i_RST = self.reset,
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o_CDIVX = self.cd_sys.clk),
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AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset),
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AsyncResetSynchronizer(self.cd_sys2x, ~pll.locked | self.reset),
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]
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(80e6), toolchain="trellis", with_ethernet=False,
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with_etherbone=False, with_led_chaser=True, **kwargs):
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platform = fpc_iii.Platform(toolchain=toolchain)
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# Serial -----------------------------------------------------------------------------------
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if kwargs[ "uart_name" ] == "serial":
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# Defaults to USB FIFO since no real serial.
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kwargs[ "uart_name" ] = "usb_fifo"
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on FPC-III",
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ident_version = True,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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ddram = platform.request("ddram")
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self.submodules.ddrphy = ECP5DDRPHY(ddram, sys_clk_freq, clk_polarity=1) # clk_p/n swapped.
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self.ddrphy.settings.rtt_nom = "disabled"
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self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
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self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
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self.comb += ddram.vccio.eq(Replicate(C(1), ddram.vccio.nbits))
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = IS43TR16256A(sys_clk_freq, "1:2"),
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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self.comb += platform.request("dram_vtt_en").eq(0 if self.integrated_main_ram_size else 1)
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# Ethernet ---------------------------------------------------------------------------------
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if with_ethernet or with_etherbone:
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self.submodules.ethphy = LiteEthPHYMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"))
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if with_ethernet:
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self.add_ethernet(phy=self.ethphy)
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if with_etherbone:
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self.add_etherbone(phy=self.ethphy)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on FPC-III")
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parser.add_argument("--build", action="store_true", help="Build bitstream.")
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parser.add_argument("--load", action="store_true", help="Load bitstream.")
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parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use (trellis or diamond).")
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parser.add_argument("--sys-clk-freq", default=80e6, help="System clock frequency.")
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ethopts = parser.add_mutually_exclusive_group()
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ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
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ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
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sdopts = parser.add_mutually_exclusive_group()
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sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
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sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
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builder_args(parser)
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soc_core_args(parser)
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trellis_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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**soc_core_argdict(args))
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if args.with_spi_sdcard:
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soc.add_spi_sdcard()
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if args.with_sdcard:
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soc.add_sdcard()
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builder = Builder(soc, **builder_argdict(args))
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builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
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builder.build(**builder_kargs, run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".svf"))
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if __name__ == "__main__":
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main()
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