139 lines
6.0 KiB
Python
Executable File
139 lines
6.0 KiB
Python
Executable File
#!/usr/bin/env python3
|
|
|
|
#
|
|
# This file is part of LiteX-Boards.
|
|
#
|
|
# Copyright (c) 2013-2014 Sebastien Bourdeauducq <sb@m-labs.hk>
|
|
# Copyright (c) 2014-2019 Florent Kermarrec <florent@enjoy-digital.fr>
|
|
# Copyright (c) 2014 Yann Sionneau <ys@m-labs.hk>
|
|
# SPDX-License-Identifier: BSD-2-Clause
|
|
|
|
import os
|
|
import argparse
|
|
from fractions import Fraction
|
|
|
|
from migen import *
|
|
from migen.genlib.resetsync import AsyncResetSynchronizer
|
|
|
|
from litex.build.io import DDROutput
|
|
|
|
from litex_boards.platforms import minispartan6
|
|
|
|
from litex.soc.cores.clock import S6PLL
|
|
from litex.soc.integration.soc_core import *
|
|
from litex.soc.integration.builder import *
|
|
from litex.soc.cores.video import VideoS6HDMIPHY
|
|
from litex.soc.cores.led import LedChaser
|
|
|
|
from litedram.modules import AS4C16M16
|
|
from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
|
|
|
|
# CRG ----------------------------------------------------------------------------------------------
|
|
|
|
class _CRG(Module):
|
|
def __init__(self, platform, sys_clk_freq, sdram_rate="1:1"):
|
|
self.rst = Signal()
|
|
self.clock_domains.cd_sys = ClockDomain()
|
|
if sdram_rate == "1:2":
|
|
self.clock_domains.cd_sys2x = ClockDomain()
|
|
self.clock_domains.cd_sys2x_ps = ClockDomain(reset_less=True)
|
|
else:
|
|
self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
|
|
self.clock_domains.cd_hdmi = ClockDomain()
|
|
self.clock_domains.cd_hdmi5x = ClockDomain()
|
|
|
|
# # #
|
|
|
|
# Clk / Rst
|
|
clk32 = platform.request("clk32")
|
|
|
|
# PLL
|
|
self.submodules.pll = pll = S6PLL(speedgrade=-1)
|
|
self.comb += pll.reset.eq(self.rst)
|
|
pll.register_clkin(clk32, 32e6)
|
|
pll.create_clkout(self.cd_sys, sys_clk_freq)
|
|
if sdram_rate == "1:2":
|
|
pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
|
|
pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=90)
|
|
else:
|
|
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
|
|
#platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
|
|
pll.create_clkout(self.cd_hdmi, 1*24e6, margin=0)
|
|
pll.create_clkout(self.cd_hdmi5x, 5*24e6, margin=0)
|
|
|
|
# SDRAM clock
|
|
sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps")
|
|
self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
|
|
|
|
# BaseSoC ------------------------------------------------------------------------------------------
|
|
|
|
class BaseSoC(SoCCore):
|
|
def __init__(self, sys_clk_freq=int(80e6), sdram_rate="1:1", with_led_chaser=True,
|
|
with_video_terminal=False, with_video_framebuffer=False, **kwargs):
|
|
platform = minispartan6.Platform()
|
|
|
|
# SoCCore ----------------------------------------------------------------------------------
|
|
SoCCore.__init__(self, platform, sys_clk_freq,
|
|
ident = "LiteX SoC on MiniSpartan6",
|
|
ident_version = True,
|
|
**kwargs)
|
|
|
|
# CRG --------------------------------------------------------------------------------------
|
|
self.submodules.crg = _CRG(platform, sys_clk_freq, sdram_rate=sdram_rate)
|
|
|
|
# SDR SDRAM --------------------------------------------------------------------------------
|
|
if not self.integrated_main_ram_size:
|
|
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
|
|
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
|
|
self.add_sdram("sdram",
|
|
phy = self.sdrphy,
|
|
module = AS4C16M16(sys_clk_freq, sdram_rate),
|
|
l2_cache_size = kwargs.get("l2_size", 8192)
|
|
)
|
|
|
|
# Video ------------------------------------------------------------------------------------
|
|
if with_video_terminal or with_video_framebuffer:
|
|
self.submodules.videophy = VideoS6HDMIPHY(platform.request("hdmi_out"), clock_domain="hdmi")
|
|
if with_video_terminal:
|
|
self.add_video_terminal(phy=self.videophy, timings="640x480@75Hz", clock_domain="hdmi")
|
|
if with_video_framebuffer:
|
|
self.add_video_framebuffer(phy=self.videophy, timings="640x480@75Hz", clock_domain="hdmi")
|
|
|
|
# Leds -------------------------------------------------------------------------------------
|
|
if with_led_chaser:
|
|
self.submodules.leds = LedChaser(
|
|
pads = platform.request_all("user_led"),
|
|
sys_clk_freq = sys_clk_freq)
|
|
|
|
# Build --------------------------------------------------------------------------------------------
|
|
|
|
def main():
|
|
parser = argparse.ArgumentParser(description="LiteX SoC on MiniSpartan6")
|
|
parser.add_argument("--build", action="store_true", help="Build bitstream.")
|
|
parser.add_argument("--load", action="store_true", help="Load bitstream.")
|
|
parser.add_argument("--sys-clk-freq", default=80e6, help="System clock frequency.")
|
|
parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
|
|
viopts = parser.add_mutually_exclusive_group()
|
|
viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
|
|
viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).")
|
|
builder_args(parser)
|
|
soc_core_args(parser)
|
|
args = parser.parse_args()
|
|
|
|
soc = BaseSoC(
|
|
sys_clk_freq = int(float(args.sys_clk_freq)),
|
|
sdram_rate = args.sdram_rate,
|
|
with_video_terminal = args.with_video_terminal,
|
|
with_video_framebuffer = args.with_video_framebuffer,
|
|
**soc_core_argdict(args)
|
|
)
|
|
builder = Builder(soc, **builder_argdict(args))
|
|
builder.build(run=args.build)
|
|
|
|
if args.load:
|
|
prog = soc.platform.create_programmer()
|
|
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
|
|
|
|
if __name__ == "__main__":
|
|
main()
|