225 lines
9.5 KiB
Python
Executable File
225 lines
9.5 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2023 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2020 Paul Sajna <sajattack@gmail.com>
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# Copyright (c) 2022 Thomas Watson <twatson52@icloud.com>
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# SPDX-License-Identifier: BSD-2-Clause
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# ./analog_pocket.py --sdram-rate=1:2 --uart-name=jtag_uart --build --load
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# litex_term jtag --jtag-config=openocd_usb_blaster.cfg
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from migen import *
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from litex.gen import *
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from litex_boards.platforms import analog_pocket
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.build.io import DDROutput
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from litex.soc.cores.clock import CycloneVPLL
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from litedram.modules import AS4C32M16
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from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq, sdram_rate="1:1"):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_video = ClockDomain()
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self.cd_video_90 = ClockDomain()
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if sdram_rate == "1:2":
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self.cd_sys2x = ClockDomain()
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self.cd_sys2x_ps = ClockDomain()
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else:
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self.cd_sys_ps = ClockDomain()
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# # #
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# Clk / Rst
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clk74 = platform.request("clk74a")
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# PLL
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self.pll = pll = CycloneVPLL()
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(clk74, 74.25e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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if sdram_rate == "1:2":
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pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
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pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=180) # Idealy 90° but needs to be increased.
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else:
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_video, 25e6)
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pll.create_clkout(self.cd_video_90, 25e6, phase=90)
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# SDRAM clock
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sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps")
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self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=50e6, sdram_rate="1:1",
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with_video_terminal = False,
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with_video_framebuffer = False,
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with_video_colorbars = False,
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**kwargs):
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platform = analog_pocket.Platform()
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq, sdram_rate)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Analog Pocket", **kwargs)
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# SDR SDRAM --------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
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self.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.sdrphy,
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module = AS4C32M16(sys_clk_freq, sdram_rate),
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# Video ------------------------------------------------------------------------------------
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if with_video_colorbars or with_video_framebuffer or with_video_terminal:
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from litex.soc.interconnect import stream
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from litex.soc.cores.video import video_data_layout
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from litex.build.io import SDROutput, DDROutput
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class VideoDDRPHY(Module):
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def __init__(self, pads, clock_domain="sys"):
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self.sink = sink = stream.Endpoint(video_data_layout)
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# # #
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# Always ack Sink, no backpressure.
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self.comb += sink.ready.eq(1)
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# Drive Clk.
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self.specials += DDROutput(i1=1, i2=0, o=pads.clk, clk=ClockSignal(clock_domain+"_90"))
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# Drive Controls.
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self.specials += SDROutput(i=sink.de, o=pads.de, clk=ClockSignal(clock_domain))
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self.specials += SDROutput(i=sink.hsync, o=pads.hsync, clk=ClockSignal(clock_domain))
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self.specials += SDROutput(i=sink.vsync, o=pads.vsync, clk=ClockSignal(clock_domain))
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self.specials += SDROutput(i=Constant(0), o=pads.skip, clk=ClockSignal(clock_domain))
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# Drive Datas.
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data = Signal(24)
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for i in range(8):
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self.comb += data[ 0+i].eq(sink.b[i] & sink.de)
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self.comb += data[ 8+i].eq(sink.g[i] & sink.de)
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self.comb += data[16+i].eq(sink.r[i] & sink.de)
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for i in range(12):
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self.specials += DDROutput(
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i1 = data[12 + i],
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i2 = data[ 0 + i],
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o = pads.data[i],
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clk = ClockSignal(clock_domain)
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)
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self.videophy = VideoDDRPHY(platform.request("video"), clock_domain="video")
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if with_video_colorbars:
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self.add_video_colorbars(phy=self.videophy, timings="640x480@60Hz", clock_domain="video")
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if with_video_terminal:
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self.add_video_terminal(phy=self.videophy, timings="640x480@60Hz", clock_domain="video")
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if with_video_framebuffer:
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self.add_video_framebuffer(phy=self.videophy, timings="640x480@60Hz", clock_domain="video")
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if False:
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#./analog_pocket.py --uart-name="crossover" --with-video-framebuffer --csr-csv=csr.csv --build --load
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# litex_server --jtag --jtag-config=openocd_usb_blaster.cfg
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# litex_term crossover
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# litescope_cli -r main_vfb_dma_source_source_last
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# Add UART auto-flush.
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self.uart.add_auto_tx_flush(sys_clk_freq=sys_clk_freq, timeout=1, interval=128)
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# DMA/VTG Synchro Debug.
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from litescope import LiteScopeAnalyzer
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analyzer_signals = [
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self.video_framebuffer.dma.source.valid,
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self.video_framebuffer.dma.source.ready,
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self.video_framebuffer.dma.source.last,
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self.video_framebuffer.source.valid,
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self.video_framebuffer.source.ready,
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self.video_framebuffer.source.last,
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self.video_framebuffer.vtg_sink.valid,
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self.video_framebuffer.vtg_sink.ready,
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self.video_framebuffer.vtg_sink.last,
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]
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self.analyzer = LiteScopeAnalyzer(analyzer_signals,
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depth = 512,
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clock_domain = "sys",
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samplerate = sys_clk_freq,
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csr_csv = "analyzer.csv"
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)
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#!/usr/bin/env python3
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# import time
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#
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# from litex import RemoteClient
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#
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# bus = RemoteClient()
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# bus.open()
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#
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# # # #
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#
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# for i in range(640*10):
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# bus.write(0x40c00000 + 4*i, 0x00000000)
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# time.sleep(0.01)
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#
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# for i in range(640*10):
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# bus.write(0x40c00000 + 4*i, 0xffffffff)
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# time.sleep(0.1)
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# # # #
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# bus.close()
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=analog_pocket.Platform, description="LiteX SoC on Analog Pocket.")
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parser.add_target_argument("--sys-clk-freq", default=50e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
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viopts = parser.target_group.add_mutually_exclusive_group()
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viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal.")
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viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer.")
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viopts.add_argument("--with-video-colorbars", action="store_true", help="Enable Video Colorbars.")
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = args.sys_clk_freq,
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sdram_rate = args.sdram_rate,
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with_video_terminal = args.with_video_terminal,
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with_video_framebuffer = args.with_video_framebuffer,
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with_video_colorbars = args.with_video_colorbars,
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**parser.soc_argdict
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)
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram").replace(".sof", ".rbf"))
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if __name__ == "__main__":
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main()
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