191 lines
8.6 KiB
Python
Executable File
191 lines
8.6 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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# Build/Use:
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# ./decklink_mini_4k.py --build --load
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# litex_term jtag --jtag-config=openocd_xc7_ft232.cfg
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import os
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from migen import *
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from litex_boards.platforms import mini_4k
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from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.video import VideoS7GTPHDMIPHY
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from litedram.modules import MT41K128M16
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from litedram.phy import s7ddrphy
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from litepcie.phy.s7pciephy import S7PCIEPHY
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from litepcie.software import generate_litepcie_software
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
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self.clock_domains.cd_idelay = ClockDomain()
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self.clock_domains.cd_hdmi = ClockDomain()
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# # #
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# Clk.
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clk100 = platform.request("clk100")
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platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk100_IBUF]")
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platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets main_s7pll0_clkin]")
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# Main PLL.
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self.submodules.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(clk100, 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_idelay, 200e6, margin=1e-1) # FIXME: Re-arrange clocking.
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pll.create_clkout(self.cd_hdmi, 148.5e6, margin=2e-2) # FIXME: Use a second PLL or move to clkout0 that has fractional support.
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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# IDELAY Ctrl.
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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# SATA PLL.
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self.clock_domains.cd_sata_refclk = ClockDomain()
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self.submodules.sata_pll = sata_pll = S7PLL(speedgrade=-1)
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self.comb += sata_pll.reset.eq(self.rst)
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sata_pll.register_clkin(clk100, 100e6)
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sata_pll.create_clkout(self.cd_sata_refclk, 150e6)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCMini):
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def __init__(self, sys_clk_freq=int(100e6), with_pcie=False, with_sata=False, with_video_terminal=False, with_video_framebuffer=False, **kwargs):
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if with_video_terminal or with_video_framebuffer:
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sys_clk_freq = int(148.5e6) # FIXME: For now requires sys_clk >= video_clk.
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platform = mini_4k.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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kwargs["uart_name"] = "jtag_uart"
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on Blackmagic Decklink Mini 4K",
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT41K128M16(sys_clk_freq, "1:4"),
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# PCIe -------------------------------------------------------------------------------------
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if with_pcie:
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self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
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data_width = 128,
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bar0_size = 0x20000)
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self.add_pcie(phy=self.pcie_phy, ndmas=1)
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# SATA -------------------------------------------------------------------------------------
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if with_sata:
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from litex.build.generic_platform import Subsignal, Pins
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from litesata.phy import LiteSATAPHY
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# IOs
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_sata_io = [
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# PCIe 2 SATA Custom Adapter (With PCIe Riser / SATA cable mod).
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("pcie2sata", 0,
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Subsignal("tx_p", Pins("B7")),
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Subsignal("tx_n", Pins("A7")),
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Subsignal("rx_p", Pins("B11")),
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Subsignal("rx_n", Pins("A11")),
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),
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]
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platform.add_extension(_sata_io)
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# RefClk, Generate 150MHz from PLL.
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platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-49]")
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# PHY
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self.submodules.sata_phy = LiteSATAPHY(platform.device,
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refclk = ClockSignal("sata_refclk"),
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pads = platform.request("pcie2sata"),
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gen = "gen2",
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clk_freq = sys_clk_freq,
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data_width = 16)
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# Core
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self.add_sata(phy=self.sata_phy, mode="read+write")
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# Video ------------------------------------------------------------------------------------
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if with_video_terminal or with_video_framebuffer:
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self.submodules.videophy = VideoS7GTPHDMIPHY(platform.request("hdmi_out"),
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sys_clk_freq = sys_clk_freq,
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clock_domain = "hdmi"
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)
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if with_video_terminal:
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self.add_video_terminal(phy=self.videophy, timings="1920x1080@60Hz", clock_domain="hdmi")
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if with_video_framebuffer:
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self.add_video_framebuffer(phy=self.videophy, timings="1920x1080@60Hz", clock_domain="hdmi")
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platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-49]") # FIXME: Use GTP refclk.
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXSoCArgumentParser(description="LiteX SoC Blackmagic Decklink Mini 4K")
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target_group = parser.add_argument_group(title="Target options")
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target_group.add_argument("--build", action="store_true", help="Build bitstream.")
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target_group.add_argument("--load", action="store_true", help="Load bitstream.")
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target_group.add_argument("--sys-clk-freq", default=148.5e6, help="System clock frequency.")
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pcieopts = target_group.add_mutually_exclusive_group()
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pcieopts.add_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
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target_group.add_argument("--driver", action="store_true", help="Generate PCIe driver.")
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viopts = target_group.add_mutually_exclusive_group()
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viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
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viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).")
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pcieopts.add_argument("--with-sata", action="store_true", help="Enable SATA support (over PCIe2SATA).")
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builder_args(parser)
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soc_core_args(parser)
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vivado_build_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_pcie = args.with_pcie,
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with_sata = args.with_sata,
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with_video_terminal = args.with_video_terminal,
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with_video_framebuffer = args.with_video_framebuffer,
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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builder_kwargs = vivado_build_argdict(args)
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builder.build(**builder_kwargs, run=args.build)
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if args.driver:
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generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver"))
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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main()
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