115 lines
4.4 KiB
Python
115 lines
4.4 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform
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from litex.build.openocd import OpenOCD
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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("clk100", 0, Pins("L19"), IOStandard("LVCMOS33")),
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("user_led", 0, Pins("F8"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("C8"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("A8"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("D9"), IOStandard("LVCMOS33")),
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("user_led", 4, Pins("F9"), IOStandard("LVCMOS33")),
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("user_btn", 0, Pins("E8"), IOStandard("LVCMOS33")),
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("user_btn", 1, Pins("B8"), IOStandard("LVCMOS33")),
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("user_btn", 2, Pins("C9"), IOStandard("LVCMOS33")),
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("user_btn", 3, Pins("E9"), IOStandard("LVCMOS33")),
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("serial", 0,
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Subsignal("tx", Pins("AB18")),
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Subsignal("rx", Pins("AA18")),
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IOStandard("LVCMOS33")
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),
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("serial", 1,
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Subsignal("tx", Pins("AA20")),
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Subsignal("rx", Pins("AB20")),
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IOStandard("LVCMOS33")
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),
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# LPDDR4 (not 1.2V, uses 1.1V or 0.6V depending on J10 jumper)
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("lpddr4", 0,
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Subsignal("clk_p", Pins("Y3"), IOStandard("DIFF_SSTL12")),
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Subsignal("clk_n", Pins("Y2"), IOStandard("DIFF_SSTL12")),
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Subsignal("cke", Pins("N4"), IOStandard("SSTL12")),
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Subsignal("odt", Pins("N5"), IOStandard("SSTL12")),
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Subsignal("reset_n", Pins("P4"), IOStandard("SSTL12")),
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Subsignal("cs", Pins("N3"), IOStandard("SSTL12")),
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Subsignal("ca", Pins("L3 L5 AA4 AA3 AB3 AB2"), IOStandard("SSTL12")),
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Subsignal("dq", Pins(
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"L1 K2 K1 K3 R1 P2 P1 N2",
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"W2 Y1 AA1 AB1 R2 T1 T3 U1"),
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IOStandard("SSTL12_T_DCI")),
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Subsignal("dqs_p", Pins("M2 U2"), IOStandard("DIFF_SSTL12")),
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Subsignal("dqs_n", Pins("M1 V2"), IOStandard("DIFF_SSTL12")),
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Subsignal("dmi", Pins("M3 W1"), IOStandard("SSTL12_T_DCI")),
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Misc("SLEW=FAST"),
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),
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# RGMII Ethernet
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("eth_ref_clk", 0, Pins("C12"), IOStandard("LVCMOS33")),
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("eth_clocks", 0,
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Subsignal("tx", Pins("E17")),
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Subsignal("rx", Pins("C17")),
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IOStandard("LVCMOS33")
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),
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("eth", 0,
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Subsignal("rst_n", Pins("E16"), IOStandard("LVCMOS33")),
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Subsignal("mdio", Pins("C14"), IOStandard("LVCMOS33")),
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Subsignal("mdc", Pins("B17"), IOStandard("LVCMOS33")),
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Subsignal("rx_ctl", Pins("A16"), IOStandard("LVCMOS33")),
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Subsignal("rx_data", Pins("B16 A15 B15 A14"), IOStandard("LVCMOS33")),
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Subsignal("tx_ctl", Pins("A13"), IOStandard("LVCMOS33")),
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Subsignal("tx_data", Pins("B21 B20 A19 A18"), IOStandard("LVCMOS33")),
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),
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# HyperRAM
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("hyperram", 0,
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Subsignal("clk", Pins("AB15")), # clk_n AB16
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Subsignal("rst_n", Pins("V17")),
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Subsignal("dq", Pins("W15 AA15 AA14 W14 Y14 V15 Y16 W17")),
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Subsignal("cs_n", Pins("AA16")),
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Subsignal("rwds", Pins("Y17")),
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IOStandard("LVCMOS33")
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),
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# SD Card
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("sdcard", 0,
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Subsignal("data", Pins("D20 D19 C22 D21"), Misc("PULLUP True")),
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Subsignal("cmd", Pins("C20"), Misc("PULLUP True")),
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Subsignal("clk", Pins("D22")),
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Subsignal("cd", Pins("B22")),
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Misc("SLEW=FAST"),
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IOStandard("LVCMOS33"),
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk100"
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default_clk_period = 1e9/100e6
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def __init__(self, device="xc7k70tfbg484-1", toolchain="vivado"):
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XilinxPlatform.__init__(self, device, _io, toolchain=toolchain)
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self.toolchain.bitstream_commands = \
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["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
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self.toolchain.additional_commands = \
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["write_cfgmem -force -format bin -interface spix4 -size 16 "
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"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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def create_programmer(self):
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return OpenOCD("openocd_xc7_ft4232.cfg", "bscan_spi_xc7k70t.bit")
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
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