162 lines
5.3 KiB
Python
162 lines
5.3 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Hans Baier <hansfbaier@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.altera import AlteraPlatform
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from litex.build.altera.programmer import USBBlaster
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk
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("clk50", 0, Pins("M9"), IOStandard("3.3-V LVTTL")),
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# Button
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("key", 0, Pins("AB13"), IOStandard("3.3-V LVTTL")),
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("key", 1, Pins("V18"), IOStandard("3.3-V LVTTL")),
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# SPIFlash (MT25QL128ABA)
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("spiflash", 0,
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# clk
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Subsignal("cs_n", Pins("R4")),
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Subsignal("clk", Pins("V3")),
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Subsignal("mosi", Pins("AB4")),
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Subsignal("miso", Pins("AB3")),
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IOStandard("3.3-V LVTTL"),
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),
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# SDR SDRAM
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("sdram_clock", 0, Pins("AB11"), IOStandard("3.3-V LVTTL")),
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("sdram", 0,
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Subsignal("a", Pins(
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"P8 P7 N8 N6 U6 U7 V6 U8",
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"T8 W8 R6 T9 Y9")),
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Subsignal("ba", Pins("T7 P9")),
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Subsignal("cs_n", Pins("AB5")),
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Subsignal("cke", Pins("V9")),
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Subsignal("ras_n", Pins("AB6")),
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Subsignal("cas_n", Pins("AA7")),
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Subsignal("we_n", Pins("W9")),
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Subsignal("dq", Pins(
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"AA12 Y11 AA10 AB10 Y10 AA9 AB8 AA8",
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" U10 T10 U11 R12 U12 P12 R10 R11")),
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Subsignal("dm", Pins("AB7 V10")),
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IOStandard("3.3-V LVTTL")
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),
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]
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# The connectors are named after the daughterboard, not the core board
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# because on the different core boards the names vary, but on the
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# daughterboard they stay the same, which we need to connect the
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# daughterboard peripherals to the core board.
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# On this board J2 is U7 and J3 is U8
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_connectors = [
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("J2", {
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# odd row even row
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7: "AA2", 8: "AA1",
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9: "Y3", 10: "W2",
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11: "U1", 12: "U2",
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13: "N1", 14: "N2",
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15: "L1", 16: "L2",
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17: "G1", 18: "G2",
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19: "E2", 20: "D3",
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21: "C1", 22: "C2",
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23: "G6", 24: "H6",
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25: "G8", 26: "H8",
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27: "F7", 28: "E7",
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29: "D6", 30: "C6",
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31: "E9", 32: "D9",
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33: "B5", 34: "A5",
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35: "B6", 36: "B7",
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37: "A7", 38: "A8",
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39: "A9", 40: "A10",
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41: "B10", 42: "C9",
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43: "G10", 44: "F10",
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45: "C11", 46: "B11",
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47: "B12", 48: "A12",
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49: "E12", 50: "D12",
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51: "D13", 52: "C13",
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53: "B13", 54: "A13",
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55: "A15", 56: "A14",
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57: "B15", 58: "C15",
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59: "C16", 60: "B16",
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}),
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("J3", {
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# odd row even row
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7: "AA14", 8: "AA13",
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9: "AA15", 10: "AB15",
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11: "Y15", 12: "Y14",
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13: "AB18", 14: "AB17",
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15: "Y17", 16: "Y16",
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17: "AA18", 18: "AA17",
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19: "AA20", 20: "AA19",
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21: "Y20", 22: "Y19",
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23: "AB21", 24: "AB20",
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25: "AA22", 26: "AB22",
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27: "W22", 28: "Y22",
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29: "Y21", 30: "W21",
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31: "U22", 32: "V21",
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33: "V20", 34: "W19",
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35: "U21", 36: "U20",
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37: "R22", 38: "T22",
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39: "P22", 40: "R21",
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41: "T20", 42: "T19",
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43: "P16", 44: "P17",
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45: "N20", 46: "N21",
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47: "M21", 48: "M20",
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49: "M18", 50: "N19",
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51: "L18", 52: "L19",
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53: "M22", 54: "L22",
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55: "L17", 56: "K17",
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57: "K22", 58: "K21",
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59: "M16", 60: "N16",
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})
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(AlteraPlatform):
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default_clk_name = "clk50"
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default_clk_period = 1e9/50e6
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core_resources = [
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("user_led", 0, Pins("D17"), IOStandard("3.3-V LVTTL")),
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("serial", 0,
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Subsignal("tx", Pins("J3:7"), IOStandard("3.3-V LVTTL")),
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Subsignal("rx", Pins("J3:8"), IOStandard("3.3-V LVTTL"))
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),
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]
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def __init__(self, toolchain="quartus", with_daughterboard=False):
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device = "5CEFA2F23C8"
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io = _io
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connectors = _connectors
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if with_daughterboard:
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from litex_boards.platforms.qmtech_daughterboard import QMTechDaughterboard
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daughterboard = QMTechDaughterboard(IOStandard("3.3-V LVTTL"))
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io += daughterboard.io
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connectors += daughterboard.connectors
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else:
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io += self.core_resources
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AlteraPlatform.__init__(self, device, io, connectors, toolchain=toolchain)
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if with_daughterboard:
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# ethernet takes the config pin, so make it available
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self.add_platform_command("set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION \"USE AS REGULAR IO\"")
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# Generate PLL clock in STA
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self.toolchain.additional_sdc_commands.append("derive_pll_clocks")
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# Calculates clock uncertainties
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self.toolchain.additional_sdc_commands.append("derive_clock_uncertainty")
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def create_programmer(self):
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return USBBlaster()
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def do_finalize(self, fragment):
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AlteraPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
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