115 lines
4.2 KiB
Python
Executable File
115 lines
4.2 KiB
Python
Executable File
#!/usr/bin/env python3
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# This file is Copyright (c) 2020 Antmicro <www.antmicro.com>
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# License: BSD
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import argparse
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from migen import *
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from migen.genlib.io import CRG
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from litex_boards.platforms import mercury_xu5
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litedram.modules import MT40A256M16
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from litedram.phy import usddrphy
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_pll4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_clk400 = ClockDomain()
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self.clock_domains.cd_ic = ClockDomain()
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self.submodules.pll = pll = USMMCM(speedgrade=-1)
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pll.register_clkin(platform.request("clk100"), 100e6)
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pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
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pll.create_clkout(self.cd_clk400, 400e6, with_reset=False)
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self.specials += [
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Instance("BUFGCE_DIV", name="main_bufgce_div",
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p_BUFGCE_DIVIDE=4,
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i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk),
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Instance("BUFGCE", name="main_bufgce",
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i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk),
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AsyncResetSynchronizer(self.cd_clk400, ~pll.locked),
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]
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ic_reset_counter = Signal(max=64, reset=63)
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ic_reset = Signal(reset=1)
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self.sync.clk400 += \
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If(ic_reset_counter != 0,
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ic_reset_counter.eq(ic_reset_counter - 1)
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).Else(
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ic_reset.eq(0)
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)
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ic_rdy = Signal()
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ic_rdy_counter = Signal(max=64, reset=63)
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self.cd_sys.rst.reset = 1
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self.comb += self.cd_ic.clk.eq(self.cd_sys.clk)
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self.sync.ic += [
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If(ic_rdy,
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If(ic_rdy_counter != 0,
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ic_rdy_counter.eq(ic_rdy_counter - 1)
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).Else(
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self.cd_sys.rst.eq(0)
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)
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)
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]
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self.specials += [
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Instance("IDELAYCTRL", p_SIM_DEVICE="ULTRASCALE",
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i_REFCLK=ClockSignal("clk400"), i_RST=ic_reset,
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o_RDY=ic_rdy),
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AsyncResetSynchronizer(self.cd_ic, ic_reset)
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]
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCSDRAM):
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def __init__(self, sys_clk_freq=int(100e6), **kwargs):
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platform = mercury_xu5.Platform()
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# SoCSDRAM ---------------------------------------------------------------------------------
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SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# DDR4 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"),
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memtype = "DDR4",
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sim_device = "ULTRASCALE_PLUS",
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iodelay_clk_freq = 400e6,
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cmd_latency = 1,
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sys_clk_freq = sys_clk_freq)
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self.add_csr("ddrphy")
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self.add_constant("USDDRPHY", None)
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sdram_module = MT40A256M16(sys_clk_freq, "1:4")
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self.register_sdram(self.ddrphy,
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geom_settings = sdram_module.geom_settings,
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timing_settings = sdram_module.timing_settings)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Enclustra's Mercury XU5")
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builder_args(parser)
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soc_sdram_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(**soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build()
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if __name__ == "__main__":
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main()
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