144 lines
6.1 KiB
Python
Executable File
144 lines
6.1 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 Paul Sajna <sajattack@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.build.io import DDROutput
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from litex_boards.platforms import de10nano
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from litex.soc.cores.clock import CycloneVPLL
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litedram.modules import AS4C32M16
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from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
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from litevideo.terminal.core import Terminal
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, with_sdram=False, sdram_rate="1:1"):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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if sdram_rate == "1:2":
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self.clock_domains.cd_sys2x = ClockDomain()
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self.clock_domains.cd_sys2x_ps = ClockDomain(reset_less=True)
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else:
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self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
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self.clock_domains.cd_vga = ClockDomain(reset_less=True)
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# # #
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# Clk / Rst
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clk50 = platform.request("clk50")
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# PLL
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self.submodules.pll = pll = CycloneVPLL(speedgrade="-I7")
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(clk50, 50e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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if sdram_rate == "1:2":
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pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
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pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=90)
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else:
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_vga, 25e6)
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# SDRAM clock
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if with_sdram:
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sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps")
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self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(50e6), with_mister_sdram=True, with_mister_vga=False, sdram_rate="1:1", **kwargs):
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platform = de10nano.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on DE10-Nano",
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ident_version = True,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq, with_sdram=with_mister_sdram, sdram_rate=sdram_rate)
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# SDR SDRAM --------------------------------------------------------------------------------
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if with_mister_sdram and not self.integrated_main_ram_size:
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sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
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self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"))
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self.add_sdram("sdram",
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phy = self.sdrphy,
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module = AS4C32M16(sys_clk_freq, sdram_rate),
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origin = self.mem_map["main_ram"],
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size = kwargs.get("max_sdram_size", 0x40000000),
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l2_cache_size = kwargs.get("l2_size", 8192),
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l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
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l2_cache_reverse = True
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)
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# VGA terminal -----------------------------------------------------------------------------
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if with_mister_vga:
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self.submodules.terminal = terminal = Terminal()
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self.bus.add_slave("terminal", self.terminal.bus, region=SoCRegion(origin=0x30000000, size=0x10000))
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vga_pads = platform.request("vga")
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self.comb += [
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vga_pads.vsync.eq(terminal.vsync),
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vga_pads.hsync.eq(terminal.hsync),
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vga_pads.red.eq(terminal.red[2:8]),
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vga_pads.green.eq(terminal.green[2:8]),
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vga_pads.blue.eq(terminal.blue[2:8])
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]
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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self.add_csr("leds")
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on DE10-Nano")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)")
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parser.add_argument("--with-mister-sdram", action="store_true", help="Enable SDRAM with MiSTer expansion board")
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parser.add_argument("--with-mister-vga", action="store_true", help="Enable VGA with Mister expansion board")
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parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate: 1:1 Full Rate (default), 1:2 Half Rate")
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args = parser.parse_args()
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builder_args(parser)
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soc_sdram_args(parser)
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_mister_sdram = args.with_mister_sdram,
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with_mister_vga = args.with_mister_vga,
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sdram_rate = args.sdram_rate,
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**soc_sdram_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".sof"))
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if __name__ == "__main__":
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main()
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