174 lines
6.2 KiB
Python
Executable File
174 lines
6.2 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Michael T. Mayers <michael@tweakoz.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import sys
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import argparse
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from migen import *
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from litex.build.io import CRG
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from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
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from litex_boards.platforms import digilent_cmod_a7
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.interconnect import wishbone
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from litex.soc.integration.soc import colorer
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kB = 1024
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mB = 1024*kB
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.cpu_reset = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
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# # #
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plls_clk12 = platform.request("clk12")
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rst_n = platform.request("cpu_reset")
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self.comb += self.cpu_reset.eq(rst_n)
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self.submodules.pll = pll = S7MMCM(speedgrade=-1)
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self.comb += pll.reset.eq(self.cpu_reset | self.rst)
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pll.register_clkin(plls_clk12, 12e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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# AsyncSRAM ------------------------------------------------------------------------------------------
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class AsyncSRAM(Module):
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def __init__(self, platform, size):
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addr_width = size//8
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data_width = 8
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self.bus = wishbone.Interface(data_width=data_width,adr_width=addr_width)
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issiram = platform.request("issiram")
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addr = issiram.addr
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data = issiram.data
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wen = issiram.wen
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cen = issiram.cen
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########################
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tristate_data = TSTriple(data_width)
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self.specials += tristate_data.get_tristate(data)
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########################
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chip_ena = self.bus.cyc & self.bus.stb & self.bus.sel[0]
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write_ena = (chip_ena & self.bus.we)
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########################
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# external write enable,
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# external chip enable,
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# internal tristate write enable
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########################
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self.comb += [
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cen.eq(~chip_ena),
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wen.eq(~write_ena),
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tristate_data.oe.eq(write_ena)
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]
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########################
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# address and data
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########################
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self.comb += [
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addr.eq(self.bus.adr[:addr_width]),
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self.bus.dat_r.eq(tristate_data.i[:data_width]),
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tristate_data.o.eq(self.bus.dat_w[:data_width])
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]
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########################
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# generate ack
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########################
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self.sync += [
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self.bus.ack.eq(self.bus.cyc & self.bus.stb & ~self.bus.ack),
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]
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########################
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def addAsyncSram(soc, platform, name, origin, size):
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ram_bus = wishbone.Interface(data_width=soc.bus.data_width)
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ram = AsyncSRAM(platform,size)
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soc.bus.add_slave(name, ram.bus, SoCRegion(origin=origin, size=size, mode="rw"))
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soc.check_if_exists(name)
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soc.logger.info("ISSIRAM {} {} {}.".format(
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colorer(name),
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colorer("added", color="green"),
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soc.bus.regions[name]))
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setattr(soc.submodules, name, ram)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, variant="a7-35",
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toolchain="vivado",
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sys_clk_freq=int(100e6),
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with_led_chaser=True,
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ident_version=True,
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with_jtagbone=True,
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with_mapped_flash=False,
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**kwargs):
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platform = digilent_cmod_a7.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on Digilent CmodA7",
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ident_version = True,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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addAsyncSram(self,platform,"main_ram",0x40000000,512*1024)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Arty A7")
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parser.add_argument("--toolchain", default="vivado", help="Toolchain use to build (default: vivado)")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--variant", default="a7-35", help="Board variant: a7-35 (default) or a7-100")
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parser.add_argument("--sys-clk-freq", default=48e6, help="System clock frequency (default: 48MHz)")
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builder_args(parser)
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soc_core_args(parser)
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vivado_build_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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variant = args.variant,
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toolchain = args.toolchain,
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sys_clk_freq = int(float(args.sys_clk_freq)),
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**soc_core_argdict(args)
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)
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builder_argd = builder_argdict(args)
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builder = Builder(soc, **builder_argd)
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builder_kwargs = vivado_build_argdict(args) if args.toolchain == "vivado" else {}
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builder.build(**builder_kwargs, run=args.build)
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if __name__ == "__main__":
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main()
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