Sean Cross 7a24406b2e targets: fomu: fix compatibility for when a cpu is added ... Things weren't quite right for adding a CPU. This fixes that by correcting the placer arguments, memory map, and USB type. Signed-off-by: Sean Cross <sean@xobs.io>		2020-02-03 08:58:54 +08:00
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__init__.py	import: allow importing directly from litex_boards.platforms or litex_boards.targets	2019-09-03 15:30:20 +02:00
aller.py	aller/nereid/tagus: update litepcie	2020-01-21 21:26:23 +01:00
c10lprefkit.py	targets: cleanup EthernetSoC	2020-01-16 10:28:09 +01:00
camlink_4k.py	targets: use default integrated rom/ram size passed with **kwargs from default soc_core_args	2020-01-13 15:20:37 +01:00
colorlight_5a_75b.py	colorlight_5a_75b: add disclaimer	2020-01-23 14:13:13 +01:00
fomu.py	targets: fomu: fix compatibility for when a cpu is added	2020-02-03 08:58:54 +08:00
hadbadge.py	targets: use default integrated rom/ram size passed with **kwargs from default soc_core_args	2020-01-13 15:20:37 +01:00
linsn_rv901t.py	targets/linsn_rv901t: cleanup arguments	2020-01-22 09:04:28 +01:00
nereid.py	aller/nereid/tagus: update litepcie	2020-01-21 21:26:23 +01:00
netv2.py	targets: cleanup EthernetSoC	2020-01-16 10:28:09 +01:00
orangecrab.py	targets: use default integrated rom/ram size passed with **kwargs from default soc_core_args	2020-01-13 15:20:37 +01:00
tagus.py	aller/nereid/tagus: update litepcie	2020-01-21 21:26:23 +01:00
trellisboard.py	targets: cleanup EthernetSoC	2020-01-16 10:28:09 +01:00
ulx3s.py	targets: use default integrated rom/ram size passed with **kwargs from default soc_core_args	2020-01-13 15:20:37 +01:00