166 lines
6.3 KiB
Python
Executable File
166 lines
6.3 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2023 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from litex.gen import *
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from litex.build.io import DDROutput
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from litex.soc.cores.clock.gowin_gw5a import GW5APLL
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.gpio import GPIOIn
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from litedram.modules import AS4C32M16, W9825G6KH6
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from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
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from litex_boards.platforms import sipeed_tang_primer_25k
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq, with_sdram=False, sdram_rate="1:2"):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_por = ClockDomain()
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if with_sdram:
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if sdram_rate == "1:2":
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self.cd_sys2x = ClockDomain()
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self.cd_sys2x_ps = ClockDomain()
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else:
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self.cd_sys_ps = ClockDomain()
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# # #
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# Clk
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clk50 = platform.request("clk50")
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# Power on reset
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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self.comb += [
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self.cd_por.clk.eq(clk50),
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por_done.eq(por_count == 0),
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]
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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# PLL
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self.pll = pll = GW5APLL(devicename=platform.devicename, device=platform.device)
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self.comb += pll.reset.eq(~por_done | self.rst)
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pll.register_clkin(clk50, 50e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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# SDRAM clock
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if with_sdram:
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if sdram_rate == "1:2":
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pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
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pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=180)
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sdram_clk = ClockSignal("sys2x_ps")
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else:
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
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sdram_clk = ClockSignal("sys_ps")
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self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=50e6,
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with_spi_flash = False,
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with_led_chaser = True,
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with_buttons = True,
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with_sdram = False,
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sdram_model = "sipeed",
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sdram_rate = "1:2",
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**kwargs):
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platform = sipeed_tang_primer_25k.Platform(toolchain="gowin")
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assert not with_sdram or (sdram_model in ["sipeed", "mister"])
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if with_sdram:
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platform.add_extension({
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"sipeed": sipeed_tang_primer_25k.sipeedSDRAM(),
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"mister": sipeed_tang_primer_25k.misterSDRAM}[sdram_model]
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)
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq, with_sdram, sdram_rate)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Tang Primer 25K", **kwargs)
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# SDR SDRAM --------------------------------------------------------------------------------
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if with_sdram and not self.integrated_main_ram_size:
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module_cls = {
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"sipeed": W9825G6KH6,
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"mister": AS4C32M16}[sdram_model]
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if sdram_rate == "1:2":
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sdrphy_cls = HalfRateGENSDRPHY
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else:
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sdrphy_cls = GENSDRPHY
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self.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.sdrphy,
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module = module_cls(sys_clk_freq, sdram_rate),
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# SPI Flash --------------------------------------------------------------------------------
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if with_spi_flash:
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from litespi.modules import W25Q64FV as SpiFlashModule
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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self.add_spi_flash(mode="1x", module=SpiFlashModule(Codes.READ_1_1_1))
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("led"),
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sys_clk_freq = sys_clk_freq
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)
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# Buttons ----------------------------------------------------------------------------------
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if with_buttons:
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self.buttons = GPIOIn(pads=~platform.request_all("btn_n"))
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=sipeed_tang_primer_25k.Platform, description="LiteX SoC on Tang Primer 25K.")
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parser.add_target_argument("--flash", action="store_true", help="Flash Bitstream.")
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parser.add_target_argument("--sys-clk-freq", default=50e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
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parser.add_target_argument("--with-sdram", action="store_true", help="Enable optional SDRAM module.")
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parser.add_target_argument("--sdram-model", default="sipeed", help="SDRAM module model.",
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choices=[
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"sipeed",
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"mister"
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])
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = args.sys_clk_freq,
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with_spi_flash = args.with_spi_flash,
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with_sdram = args.with_sdram,
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sdram_model = args.sdram_model,
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**parser.soc_argdict
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)
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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main()
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