225 lines
6.9 KiB
Python
225 lines
6.9 KiB
Python
# This file is Copyright (c) 2019 Vamsi K Vytla <vamsi.vytla@gmail.com>
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# License: BSD
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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("user_led", 0, Pins("M26"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("T24"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("T25"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("R26"), IOStandard("LVCMOS33")),
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("cpu_reset", 0, Pins("U4"), IOStandard("SSTL15")),
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("clk200", 0,
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Subsignal("p", Pins("R3"), IOStandard("DIFF_SSTL15")),
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Subsignal("n", Pins("P3"), IOStandard("DIFF_SSTL15"))
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),
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("clk156", 0,
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Subsignal("p", Pins("M21"), IOStandard("LVDS_25")),
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Subsignal("n", Pins("M22"), IOStandard("LVDS_25"))
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),
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("serial", 0,
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Subsignal("cts", Pins("V19")),
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Subsignal("rts", Pins("W19")),
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Subsignal("tx", Pins("U19")),
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Subsignal("rx", Pins("T19")),
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IOStandard("LVCMOS18")
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),
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("eth_clocks", 0,
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Subsignal("tx", Pins("U22")),
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Subsignal("rx", Pins("U21")),
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IOStandard("LVCMOS18")
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),
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("eth", 0,
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Subsignal("rx_ctl", Pins("U14")),
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Subsignal("rx_data", Pins("U17 V17 V16 V14")),
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Subsignal("tx_ctl", Pins("T15")),
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Subsignal("tx_data", Pins("U16 U15 T18 T17")),
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Subsignal("rst_n", Pins("V18")),
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Subsignal("mdc", Pins("W18")),
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Subsignal("mdio", Pins("T14")),
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IOStandard("LVCMOS18"), Misc("SLEW=FAST"), Drive(16)
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),
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("ddram", 0,
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Subsignal("a", Pins(
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"M4 J3 J1 L4 K5 M7 K1 M6",
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"H1 K3 N7 L5 L7 N6 L3 K2"),
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IOStandard("SSTL15")),
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Subsignal("ba", Pins("N1 M1 H2"), IOStandard("SSTL15")),
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Subsignal("ras_n", Pins("P1"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("T4"), IOStandard("SSTL15")),
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Subsignal("we_n", Pins("R1"), IOStandard("SSTL15")),
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Subsignal("cs_n", Pins("T3"), IOStandard("SSTL15")),
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Subsignal("dm", Pins("AC6 AC4 AA3 U7 G1 F3 G5 H9"),
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IOStandard("SSTL15")),
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Subsignal("dq", Pins(
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"AB6 AA8 Y8 AB5 AA5 Y5 Y6 Y7",
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"AF4 AF5 AF3 AE3 AD3 AC3 AB4 AA4",
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"AC2 AB2 AF2 AE2 Y1 Y2 AC1 AB1",
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"Y3 W3 W6 V6 W4 W5 W1 V1",
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"G2 D1 E1 E2 F2 A2 A3 C2",
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"C3 D3 A4 B4 C4 D4 D5 E5",
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"F4 G4 K6 K7 K8 L8 J5 J6",
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"G6 H6 F7 F8 G8 H8 D6 E6"),
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IOStandard("SSTL15")),
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Subsignal("dqs_p", Pins("V8 AD5 AD1 V3 C1 B5 J4 H7"),
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IOStandard("DIFF_SSTL15")),
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Subsignal("dqs_n", Pins("W8 AE5 AE1 V2 B1 A5 H4 G7"),
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IOStandard("DIFF_SSTL15")),
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Subsignal("clk_p", Pins("M2"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_n", Pins("L2"), IOStandard("DIFF_SSTL15")),
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Subsignal("cke", Pins("P4"), IOStandard("SSTL15")),
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Subsignal("odt", Pins("R2"), IOStandard("SSTL15")),
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Subsignal("reset_n", Pins("N8"), IOStandard("LVCMOS15"))
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),
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("vadj_on_b", 0, Pins("R16"), IOStandard("LVCMOS25")),
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("gtp_refclk", 0,
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Subsignal("p", Pins("AA13")),
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Subsignal("n", Pins("AB13"))
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),
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("sfp", 0,
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Subsignal("txp", Pins("AC10")),
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Subsignal("txn", Pins("AD10")),
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Subsignal("rxp", Pins("AC12")),
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Subsignal("rxn", Pins("AD12")),
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),
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("sfp_mgt_clk_sel0", 0, Pins("B26"), IOStandard("LVCMOS25")),
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("sfp_mgt_clk_sel1", 0, Pins("C24"), IOStandard("LVCMOS25")),
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("sfp_tx_disable_n", 0, Pins("R18"), IOStandard("LVCMOS33")),
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("sfp_rx_los", 0, Pins("R23"), IOStandard("LVCMOS33")),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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("HPC", {
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"CLK0_M2C_N": "C19",
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"CLK0_M2C_P": "D19",
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"CLK1_M2C_N": "H22",
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"CLK1_M2C_P": "H21",
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"LA00_CC_N": "C18",
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"LA00_CC_P": "D18",
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"LA01_CC_N": "E18",
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"LA01_CC_P": "E17",
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"LA02_N": "H15",
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"LA02_P": "H14",
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"LA03_N": "F17",
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"LA03_P": "G17",
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"LA04_N": "F19",
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"LA04_P": "F18",
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"LA05_N": "F15",
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"LA05_P": "G15",
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"LA06_N": "F20",
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"LA06_P": "G19",
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"LA07_N": "G16",
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"LA07_P": "H16",
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"LA08_N": "B17",
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"LA08_P": "C17",
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"LA09_N": "D16",
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"LA09_P": "E16",
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"LA10_N": "A18",
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"LA10_P": "A17",
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"LA11_N": "A19",
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"LA11_P": "B19",
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"LA12_N": "D20",
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"LA12_P": "E20",
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"LA13_N": "A20",
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"LA13_P": "B20",
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"LA14_N": "B21",
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"LA14_P": "C21",
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"LA15_N": "A22",
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"LA15_P": "B22",
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"LA16_N": "D21",
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"LA16_P": "E21",
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"LA17_CC_N": "J21",
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"LA17_CC_P": "K21",
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"LA18_CC_N": "G21",
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"LA18_CC_P": "G20",
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"LA19_N": "L14",
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"LA19_P": "M14",
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"LA20_N": "M17",
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"LA20_P": "M16",
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"LA21_N": "H19",
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"LA21_P": "J19",
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"LA22_N": "L18",
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"LA22_P": "L17",
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"LA23_N": "J20",
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"LA23_P": "K20",
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"LA24_N": "H18",
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"LA24_P": "J18",
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"LA25_N": "F22",
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"LA25_P": "G22",
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"LA26_N": "H24",
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"LA26_P": "J24",
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"LA27_N": "E23",
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"LA27_P": "F23",
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"LA28_N": "K23",
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"LA28_P": "K22",
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"LA29_N": "F24",
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"LA29_P": "G24",
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"LA30_N": "D25",
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"LA30_P": "E25",
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"LA31_N": "D26",
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"LA31_P": "E26",
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"LA32_N": "G26",
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"LA32_P": "H26",
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"LA33_N": "F25",
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"LA33_P": "G25",
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"PRSNT_M2C_L": "N16",
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"PWR_GOOD_FLASH_RST_B": "P15"}
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),
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("XADC", {
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"GPIO0": "H17",
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"GPIO1": "E22",
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"GPIO2": "K18",
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"GPIO3": "L19",
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"VAUX0_N": "J16",
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"VAUX0_P": "K15",
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"VAUX8_N": "J15",
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"VAUX8_P": "J14",
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}
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk156"
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default_clk_period = 6.4
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def __init__(self):
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XilinxPlatform.__init__(self, "xc7a200t-fbg676-2", _io, _connectors, toolchain="vivado")
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self.toolchain.bitstream_commands = ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
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self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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def create_programmer(self):
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return VivadoProgrammer()
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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try:
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self.add_period_constraint(self.lookup_request("clk200").p, 1e9/200e6)
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except ConstraintError:
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pass
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try:
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self.add_period_constraint(self.lookup_request("eth_clocks").rx, 1e9/125e6)
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except ConstraintError:
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pass
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try:
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self.add_period_constraint(self.lookup_request("eth_clocks").tx, 1e9/125e6)
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except ConstraintError:
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pass
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