123 lines
4.8 KiB
Python
Executable File
123 lines
4.8 KiB
Python
Executable File
#!/usr/bin/env python3
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# This file is Copyright (c) 2019 Antti Lukats <antti.lukats@gmail.com>
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# This file is Copyright (c) 2019 msloniewski <marcin.sloniewski@gmail.com>
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# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import os
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import argparse
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from migen import *
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from litex_boards.platforms import c10lprefkit
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from litex.soc.cores.clock import Cyclone10LPPLL
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litedram.modules import MT48LC16M16
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from litedram.phy import GENSDRPHY
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from liteeth.phy.mii import LiteEthPHYMII
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from litehyperbus.core.hyperbus import HyperRAM
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
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# # #
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# Clk / Rst
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clk12 = platform.request("clk12")
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# PLL
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self.submodules.pll = pll = Cyclone10LPPLL(speedgrade="-A7")
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self.comb += pll.reset.eq(~platform.request("cpu_reset"))
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pll.register_clkin(clk12, 12e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
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# SDRAM clock
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self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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mem_map = {
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"hyperram": 0x20000000,
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}
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mem_map.update(SoCCore.mem_map)
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def __init__(self, sys_clk_freq=int(50e6), with_ethernet=False, **kwargs):
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platform = c10lprefkit.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on C10 LP RefKit",
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ident_version = True,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# HyperRam ---------------------------------------------------------------------------------
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self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
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self.add_wb_slave(self.mem_map["hyperram"], self.hyperram.bus)
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self.add_memory_region("hyperram", self.mem_map["hyperram"], 8*1024*1024)
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# SDR SDRAM --------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
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self.add_sdram("sdram",
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phy = self.sdrphy,
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module = MT48LC16M16(sys_clk_freq, "1:1"),
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origin = self.mem_map["main_ram"],
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size = kwargs.get("max_sdram_size", 0x40000000),
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l2_cache_size = kwargs.get("l2_size", 8192),
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l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
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l2_cache_reverse = True
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)
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# Ethernet ---------------------------------------------------------------------------------
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if with_ethernet:
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self.submodules.ethphy = LiteEthPHYMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"))
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self.add_csr("ethphy")
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self.add_ethernet(phy=self.ethphy)
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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self.add_csr("leds")
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on C10 LP RefKit")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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builder_args(parser)
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soc_sdram_args(parser)
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parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
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args = parser.parse_args()
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soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".sof"))
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if __name__ == "__main__":
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main()
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