Florent Kermarrec f9619c4a8f aller/tagus/nereid: use crossover UART, rename SoC to PCIe SoC and pass soc_sdram_argdict to PCIeSoC		2020-01-16 10:51:35 +01:00
..
__init__.py	import: allow importing directly from litex_boards.platforms or litex_boards.targets	2019-09-03 15:30:20 +02:00
aller.py	aller/tagus/nereid: use crossover UART, rename SoC to PCIe SoC and pass soc_sdram_argdict to PCIeSoC	2020-01-16 10:51:35 +01:00
c10lprefkit.py	targets: cleanup EthernetSoC	2020-01-16 10:28:09 +01:00
camlink_4k.py	targets: use default integrated rom/ram size passed with **kwargs from default soc_core_args	2020-01-13 15:20:37 +01:00
fomu.py	travis: update/fix	2020-01-13 17:00:01 +01:00
hadbadge.py	targets: use default integrated rom/ram size passed with **kwargs from default soc_core_args	2020-01-13 15:20:37 +01:00
nereid.py	aller/tagus/nereid: use crossover UART, rename SoC to PCIe SoC and pass soc_sdram_argdict to PCIeSoC	2020-01-16 10:51:35 +01:00
netv2.py	targets: cleanup EthernetSoC	2020-01-16 10:28:09 +01:00
orangecrab.py	targets: use default integrated rom/ram size passed with **kwargs from default soc_core_args	2020-01-13 15:20:37 +01:00
tagus.py	aller/tagus/nereid: use crossover UART, rename SoC to PCIe SoC and pass soc_sdram_argdict to PCIeSoC	2020-01-16 10:51:35 +01:00
trellisboard.py	targets: cleanup EthernetSoC	2020-01-16 10:28:09 +01:00
ulx3s.py	targets: use default integrated rom/ram size passed with **kwargs from default soc_core_args	2020-01-13 15:20:37 +01:00